SPI_DEVICE/2P Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.313m	645.934ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.380s	22.466us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.690s	130.891us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.630s	2.424ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.920s	5.032ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.500s	59.339us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.690s	130.891us	20	20	100.00
		spi_device_csr_aliasing	25.920s	5.032ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	31.835us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.340s	26.817us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.840s	24.220us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	27.791us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	19.158us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	15.230s	557.593us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	15.230s	557.593us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	34.540s	13.317ms	50	50	100.00
		spi_device_tpm_sts_read	1.410s	244.563us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.091m	12.042ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.440s	14.126ms	50	50	100.00
		spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.520s	54.985ms	50	50	100.00
		spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.520s	54.985ms	50	50	100.00
		spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	16.400s	5.077ms	50	50	100.00
		spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	16.400s	5.077ms	50	50	100.00
		spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	16.400s	5.077ms	50	50	100.00
		spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	16.400s	5.077ms	50	50	100.00
		spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	16.400s	5.077ms	50	50	100.00
		spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	51.210s	83.053ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.043m	183.739ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.043m	183.739ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.043m	183.739ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.051m	12.664ms	50	50	100.00
		spi_device_read_buffer_direct	7.920s	7.100ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.043m	183.739ms	50	50	100.00
		spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	9.808m	122.200ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.020s	6.077ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.020s	6.077ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.313m	645.934ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.736m	118.699ms	49	50	98.00
V2	stress_all	spi_device_stress_all	21.042m	162.812ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.780s	21.458us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	15.335us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.110s	1.129ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.110s	1.129ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.380s	22.466us	5	5	100.00
		spi_device_csr_rw	2.690s	130.891us	20	20	100.00
		spi_device_csr_aliasing	25.920s	5.032ms	5	5	100.00
		spi_device_same_csr_outstanding	4.580s	614.537us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.380s	22.466us	5	5	100.00
		spi_device_csr_rw	2.690s	130.891us	20	20	100.00
		spi_device_csr_aliasing	25.920s	5.032ms	5	5	100.00
		spi_device_same_csr_outstanding	4.580s	614.537us	20	20	100.00
V2		TOTAL			977	980	99.69
V2S	tl_intg_err	spi_device_sec_cm	1.250s	171.820us	5	5	100.00
		spi_device_tl_intg_err	22.070s	9.644ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.070s	9.644ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1116	1120	99.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	19	86.36
V2S	2	2	2	100.00
V3	1	0	0	0.00

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1024) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

23.spi_device_flash_and_tpm_min_idle.61000579693805720374924169862880920357424819795533767889602005237384814279346
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1722451118 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x89e730) != exp '{'{other_status:'h1a9072, wel:'h0, busy:'h0}}
  UVM_INFO @ 8858443815 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 1/14
  UVM_INFO @ 12054909788 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/12
  UVM_INFO @ 20732714100 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/14
  UVM_INFO @ 29275090907 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/12

Test spi_device_stress_all has 1 failures.

36.spi_device_stress_all.89968096932547543752461017841480846208343336466146656348418933065213967878542
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 103214435654 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x7201a0) != exp '{'{other_status:'h1c8068, wel:'h0, busy:'h1}}
  UVM_INFO @ 104264155654 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 0/17
  UVM_INFO @ 104269795654 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 1/12
  UVM_INFO @ 105335454888 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/17
  UVM_INFO @ 105469875654 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/12

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

31.spi_device_flash_and_tpm.79970989941827156707798778998205242353707128452238264779006157712915176459294
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/31.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 10840771109 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 10955563837 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/16
  UVM_INFO @ 11933283089 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/18
  UVM_INFO @ 11993687065 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/16
  UVM_INFO @ 13608240652 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/16

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_all has 1 failures.

45.spi_device_flash_all.3744087554233765021322172536555505567063931752804326749965025853566069516969
Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/45.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 7050538255 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 7129190687 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 15/16
  UVM_INFO @ 7780410007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job spi_device-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": stat /workspace/mnt/input/cov_merge: too many levels of symbolic links has 1 failures:
- Test spi_device has 1 failures.
  - cov_report
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/cov_report/cov_report.log
```
  Job ID: smart:a910ce24-fff8-40cc-9c3b-39cd558d7863
```