SPI_DEVICE/1R1W Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.979m	1.028s	48	50	96.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.150s	35.039us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.830s	185.509us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.920s	1.070ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.930s	1.897ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.760s	173.453us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.830s	185.509us	20	20	100.00
		spi_device_csr_aliasing	23.930s	1.897ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	10.529us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.810s	49.088us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	csb_read	spi_device_csb_read	0.880s	36.253us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.160s	114.140us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	38.831us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	8.390s	463.600us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.390s	463.600us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	32.530s	24.103ms	50	50	100.00
		spi_device_tpm_sts_read	1.320s	136.333us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	55.540s	10.146ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	55.440s	89.597ms	50	50	100.00
		spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	51.850s	39.828ms	50	50	100.00
		spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	51.850s	39.828ms	50	50	100.00
		spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	17.460s	5.453ms	50	50	100.00
		spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	17.460s	5.453ms	50	50	100.00
		spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	17.460s	5.453ms	50	50	100.00
		spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	17.460s	5.453ms	50	50	100.00
		spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	17.460s	5.453ms	50	50	100.00
		spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	50.980s	36.072ms	49	50	98.00
V2	mailbox_command	spi_device_mailbox	54.690s	128.243ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	54.690s	128.243ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	54.690s	128.243ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.074m	25.443ms	46	50	92.00
		spi_device_read_buffer_direct	7.110s	3.611ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	54.690s	128.243ms	50	50	100.00
		spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.883m	543.759ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	15.070s	4.563ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	15.070s	4.563ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.979m	1.028s	48	50	96.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.093m	153.103ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.015m	539.951ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.780s	27.576us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	23.393us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.630s	228.254us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.630s	228.254us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.150s	35.039us	5	5	100.00
		spi_device_csr_rw	2.830s	185.509us	20	20	100.00
		spi_device_csr_aliasing	23.930s	1.897ms	5	5	100.00
		spi_device_same_csr_outstanding	4.370s	210.654us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.150s	35.039us	5	5	100.00
		spi_device_csr_rw	2.830s	185.509us	20	20	100.00
		spi_device_csr_aliasing	23.930s	1.897ms	5	5	100.00
		spi_device_same_csr_outstanding	4.370s	210.654us	20	20	100.00
V2		TOTAL			974	980	99.39
V2S	tl_intg_err	spi_device_sec_cm	1.000s	197.722us	5	5	100.00
		spi_device_tl_intg_err	25.520s	4.016ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.520s	4.016ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1112	1120	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	19	86.36
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.38	94.43	98.61	89.36	97.10	95.82	98.22

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 3 failures:
- Test spi_device_flash_mode has 3 failures.
  - 10.spi_device_flash_mode.16992432158954585444017618908031721780038211620348410225567728730018014485515
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 554152251 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 1150313463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.spi_device_flash_mode.49436078832375504711089491465975307414438770135773429490725288468067084215962
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/16.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 10931723736 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 12901072784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 2 failures:

Test spi_device_flash_and_tpm has 1 failures.

22.spi_device_flash_and_tpm.84895882554159081264773808683425992304360965589965005454061070067732013727207
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 2593378021 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 2961881706 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/20
  UVM_INFO @ 3663612572 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/6
  UVM_INFO @ 4278349416 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/20
  UVM_INFO @ 5486406951 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/20

Test spi_device_stress_all has 1 failures.

49.spi_device_stress_all.105582118463369391807888797256436887126607102829362760511653438708576457221711
Line 311, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/49.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 328716718100 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 331629888912 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/14
  UVM_INFO @ 331819714997 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/20
  UVM_INFO @ 341413557255 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 7/20
  UVM_INFO @ 346475182775 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/14

UVM_ERROR (spi_device_scoreboard.sv:1024) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

3.spi_device_flash_and_tpm.18109257865488918459657249936800248477309062551823909814133030520949845533247
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 919621079 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x67f984) != exp '{'{other_status:'h10a598, wel:'h0, busy:'h0}}
  UVM_INFO @ 999568702 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/10
  UVM_INFO @ 1514226207 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/18
  UVM_INFO @ 2489224459 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/10
  UVM_INFO @ 2574958973 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/18

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [spi_device_upload_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_upload has 1 failures.

15.spi_device_upload.90173453789319591678594305247767165932795438727202993650275920971218314725370
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_upload/latest/run.log

  UVM_ERROR @ 290887258 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 299255078 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 7, test op = 0xe1
  UVM_INFO @ 318708464 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 8, test op = 0x5
  UVM_INFO @ 342844828 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 9, test op = 0xa8
  UVM_INFO @ 344849704 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 10, test op = 0xf4

UVM_FATAL (spi_device_scoreboard.sv:891) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 34.spi_device_flash_mode.61864878512186790144653204774203914027449694820571751025961203158116543902091
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 42830716433 ps: (spi_device_scoreboard.sv:891) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 42830716433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```