SPI_DEVICE/2P Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.921m	870.301ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.390s	77.056us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.870s	668.608us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.770s	10.822ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.500s	10.006ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.960s	199.833us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.870s	668.608us	20	20	100.00
		spi_device_csr_aliasing	23.500s	10.006ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	11.963us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.760s	105.106us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.820s	85.636us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.140s	84.482us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	24.248us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	9.740s	2.498ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.740s	2.498ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	38.720s	107.355ms	50	50	100.00
		spi_device_tpm_sts_read	1.280s	207.390us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.456m	32.113ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.610s	56.187ms	50	50	100.00
		spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	45.220s	16.566ms	50	50	100.00
		spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	45.220s	16.566ms	50	50	100.00
		spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	cmd_info_slots	spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	cmd_read_status	spi_device_intercept	12.520s	3.802ms	50	50	100.00
		spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	cmd_read_jedec	spi_device_intercept	12.520s	3.802ms	50	50	100.00
		spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	cmd_read_sfdp	spi_device_intercept	12.520s	3.802ms	50	50	100.00
		spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	cmd_fast_read	spi_device_intercept	12.520s	3.802ms	50	50	100.00
		spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	cmd_read_pipeline	spi_device_intercept	12.520s	3.802ms	50	50	100.00
		spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	flash_cmd_upload	spi_device_upload	58.950s	83.888ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	54.460s	71.743ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	54.460s	71.743ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	54.460s	71.743ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	54.320s	17.726ms	49	50	98.00
		spi_device_read_buffer_direct	7.830s	25.749ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	54.460s	71.743ms	50	50	100.00
		spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	quad_spi	spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	dual_spi	spi_device_flash_all	8.426m	244.503ms	48	50	96.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.730s	5.921ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.730s	5.921ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.921m	870.301ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.657m	78.294ms	48	50	96.00
V2	stress_all	spi_device_stress_all	11.249m	356.603ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	12.830us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	19.587us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.940s	62.797us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.940s	62.797us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.390s	77.056us	5	5	100.00
		spi_device_csr_rw	2.870s	668.608us	20	20	100.00
		spi_device_csr_aliasing	23.500s	10.006ms	5	5	100.00
		spi_device_same_csr_outstanding	4.720s	444.827us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.390s	77.056us	5	5	100.00
		spi_device_csr_rw	2.870s	668.608us	20	20	100.00
		spi_device_csr_aliasing	23.500s	10.006ms	5	5	100.00
		spi_device_same_csr_outstanding	4.720s	444.827us	20	20	100.00
V2		TOTAL			975	980	99.49
V2S	tl_intg_err	spi_device_sec_cm	1.200s	182.087us	5	5	100.00
		spi_device_tl_intg_err	21.090s	1.332ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.090s	1.332ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1115	1120	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	19	86.36
V2S	2	2	2	100.00
V3	1	0	0	0.00

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1024) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 2 failures:

Test spi_device_flash_all has 1 failures.

14.spi_device_flash_all.86876452123099425676083196640069641156154978300550512559830141380476500485152
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 6440684560 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5cf644) != exp '{'{other_status:'h15034c, wel:'h0, busy:'h0}}
  UVM_INFO @ 6926264560 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/19
  UVM_INFO @ 12003579560 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/19
  UVM_INFO @ 16348610560 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/19
  UVM_INFO @ 19157222560 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/19

Test spi_device_flash_and_tpm_min_idle has 1 failures.

19.spi_device_flash_and_tpm_min_idle.67327532776889468984239778078897864433697675680395424039075703142394367050097
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1925016782 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa16d3c) != exp '{'{other_status:'h37427, wel:'h0, busy:'h0}}
  UVM_INFO @ 2138668032 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/14
  UVM_INFO @ 2202096782 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 7/7
  UVM_INFO @ 2406509782 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 6/14
  UVM_INFO @ 2824524032 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 7/14

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

20.spi_device_flash_and_tpm_min_idle.26403560449128800128006428408502435459184574411529762635221374423406022251031
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 696376861 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 837721137 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/14
  UVM_INFO @ 976582965 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/14
  UVM_INFO @ 1125249381 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/14
  UVM_INFO @ 1420941965 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 6/14

UVM_ERROR (spi_device_scoreboard.sv:477) [scoreboard] Check failed flash_status_q.size <= * (* [*] vs * [*]) has 1 failures:

Test spi_device_flash_all has 1 failures.

42.spi_device_flash_all.105477088643362135493723465058997575498446534794755494970760519434620221660379
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/42.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 9123226265 ps: (spi_device_scoreboard.sv:477) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 9445418597 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/9
  UVM_INFO @ 14273047207 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/9
  UVM_INFO @ 16976061229 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/9
  UVM_INFO @ 18559916589 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/9

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 46.spi_device_flash_mode.99332926828226981495479676947162475601015825064145411665242351490481210165264
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/46.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 1081008596 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 2048599630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job spi_device-sim-vcs_cov_report killed due to: Exit reason: Job lost from admin server: generic::not_found: generic::not_found: job is not found has 1 failures:
- Test spi_device has 1 failures.
  - cov_report
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/cov_report/cov_report.log
```
  Job ID: smart:c911b076-0713-4841-8fc3-c328d6ad4b5b
```