e844018f2c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | spi_device_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | spi_device_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 0 | 20 | 0.00 | ||
| spi_device_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | spi_device_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | spi_device_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 115 | 0.00 | |||
| V2 | csb_read | spi_device_csb_read | 0 | 50 | 0.00 | ||
| V2 | mem_parity | spi_device_mem_parity | 0 | 20 | 0.00 | ||
| V2 | mem_cfg | spi_device_ram_cfg | 0 | 20 | 0.00 | ||
| V2 | tpm_read | spi_device_tpm_rw | 0 | 50 | 0.00 | ||
| V2 | tpm_write | spi_device_tpm_rw | 0 | 50 | 0.00 | ||
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 0 | 50 | 0.00 | ||
| spi_device_tpm_sts_read | 0 | 50 | 0.00 | ||||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 0 | 50 | 0.00 | ||
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_info_slots | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | cmd_read_status | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_read_jedec | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_read_sfdp | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_fast_read | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_read_pipeline | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | flash_cmd_upload | spi_device_upload | 0 | 50 | 0.00 | ||
| V2 | mailbox_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | cmd_read_buffer | spi_device_flash_mode | 0 | 50 | 0.00 | ||
| spi_device_read_buffer_direct | 0 | 50 | 0.00 | ||||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | quad_spi | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | dual_spi | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 0 | 50 | 0.00 | ||
| V2 | write_enable_disable | spi_device_cfg_cmd | 0 | 50 | 0.00 | ||
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 0 | 50 | 0.00 | ||
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 0 | 50 | 0.00 | ||
| V2 | stress_all | spi_device_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | spi_device_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | spi_device_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | spi_device_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 0 | 5 | 0.00 | ||
| spi_device_csr_rw | 0 | 20 | 0.00 | ||||
| spi_device_csr_aliasing | 0 | 5 | 0.00 | ||||
| spi_device_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 0 | 5 | 0.00 | ||
| spi_device_csr_rw | 0 | 20 | 0.00 | ||||
| spi_device_csr_aliasing | 0 | 5 | 0.00 | ||||
| spi_device_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 980 | 0.00 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 0 | 5 | 0.00 | ||
| spi_device_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 0 | 1120 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 22 | 22 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 0 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1122 failures:
0.spi_device_csb_read.99023426650287875659728566125249825205453111074060802158440347752967265454924
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_csb_read/latest/run.log
1.spi_device_csb_read.16209620942896469175331301124871587453007671894320162765185494714782435862524
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_csb_read/latest/run.log
... and 48 more failures.
0.spi_device_mem_parity.950401868315553588910237024626461398672451900267156156083491270061590661092
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_mem_parity/latest/run.log
1.spi_device_mem_parity.92403187814177585245632181013656636437535543544461923989746118738962438621660
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_mem_parity/latest/run.log
... and 18 more failures.
0.spi_device_ram_cfg.52694948563906993117757752062133283344797943714076904710255700524942204416943
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_ram_cfg/latest/run.log
1.spi_device_ram_cfg.46002885741543937435829636367186636278870484001640257270807432785329043993983
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_ram_cfg/latest/run.log
... and 18 more failures.
0.spi_device_tpm_read_hw_reg.107742265137862394520177170779744806841515268944529540050096246668718642746895
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_tpm_read_hw_reg/latest/run.log
1.spi_device_tpm_read_hw_reg.105266072212328700387377868151092033452135565484203465451211004860609465378788
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_tpm_read_hw_reg/latest/run.log
... and 48 more failures.
0.spi_device_tpm_all.105180044595632617801722523832768792788652253385051548790322755771571267753651
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_tpm_all/latest/run.log
1.spi_device_tpm_all.19103176223210049807290544878066830430370505821518348464137607253032598865730
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_tpm_all/latest/run.log
... and 48 more failures.
Copying gs://7fa5dc6d-7dd3-3f84-9a7e-4f1238163bf8/EDAFarmArchive/tarballs/*/*/*/*/opentitan1_cluster:smart-*-aeea-4ec7-*-aa0fc740a965/output.tar.gz... / [* files][ * B/ * MiB] Tracker file doesn't match for download of /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/default/output.tar.gz. Restarting download from scratch. OSError: No such file or directory. - has 1 failures:
gzip: stdin: decompression OK, trailing garbage ignored tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures: