SPI_DEVICE/2P Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: `e844018f2c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	15.029m	520.789ms	48	50	96.00
V1	csr_hw_reset	spi_device_csr_hw_reset			0	5	0.00
V1	csr_rw	spi_device_csr_rw			0	20	0.00
V1	csr_bit_bash	spi_device_csr_bit_bash			0	5	0.00
V1	csr_aliasing	spi_device_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw			0	20	0.00
		spi_device_csr_aliasing			0	5	0.00
V1	mem_walk	spi_device_mem_walk			0	5	0.00
V1	mem_partial_access	spi_device_mem_partial_access			0	5	0.00
V1		TOTAL			48	115	41.74
V2	csb_read	spi_device_csb_read	0.900s	17.652us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	32.112us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	18.758us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	12.370s	1.359ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.370s	1.359ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	34.690s	13.518ms	50	50	100.00
		spi_device_tpm_sts_read	1.260s	149.246us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.259m	50.299ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	36.720s	12.140ms	50	50	100.00
		spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	45.400s	75.203ms	50	50	100.00
		spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	45.400s	75.203ms	50	50	100.00
		spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	14.250s	4.498ms	50	50	100.00
		spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	14.250s	4.498ms	50	50	100.00
		spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	14.250s	4.498ms	50	50	100.00
		spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	14.250s	4.498ms	50	50	100.00
		spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	14.250s	4.498ms	50	50	100.00
		spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	55.940s	35.671ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	57.610s	50.250ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	57.610s	50.250ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	57.610s	50.250ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	52.130s	10.787ms	48	50	96.00
		spi_device_read_buffer_direct	6.600s	1.829ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	57.610s	50.250ms	50	50	100.00
		spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.838m	876.546ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.970s	6.162ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.970s	6.162ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	15.029m	520.789ms	48	50	96.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.215m	82.287ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.469m	952.959ms	48	50	96.00
V2	alert_test	spi_device_alert_test	0.840s	19.763us	50	50	100.00
V2	intr_test	spi_device_intr_test			0	50	0.00
V2	tl_d_oob_addr_access	spi_device_tl_errors			0	20	0.00
V2	tl_d_illegal_access	spi_device_tl_errors			0	20	0.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset			0	5	0.00
		spi_device_csr_rw			0	20	0.00
		spi_device_csr_aliasing			0	5	0.00
		spi_device_same_csr_outstanding			0	20	0.00
V2	tl_d_partial_access	spi_device_csr_hw_reset			0	5	0.00
		spi_device_csr_rw			0	20	0.00
		spi_device_csr_aliasing			0	5	0.00
		spi_device_same_csr_outstanding			0	20	0.00
V2		TOTAL			886	980	90.41
V2S	tl_intg_err	spi_device_sec_cm	1.200s	88.525us	5	5	100.00
		spi_device_tl_intg_err			0	20	0.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err			0	20	0.00
V2S		TOTAL			5	25	20.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			939	1120	83.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	0	0.00
V2	22	22	17	77.27
V2S	2	2	1	50.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.94	98.37	93.30	98.21	89.36	97.03	86.17	95.10

Failure Buckets

Job killed most likely because its dependent job failed. has 175 failures:
- Test spi_device_tl_errors has 20 failures.
  - 0.spi_device_tl_errors.61733879882521818812727902242787245075915978788283517941783266844978165258092
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_tl_errors/latest/run.log
  - 1.spi_device_tl_errors.100813400632459831620894091889261633277025406982069467863837271019412779243915
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_tl_errors/latest/run.log
  - ... and 18 more failures.
- Test spi_device_tl_intg_err has 20 failures.
  - 0.spi_device_tl_intg_err.44042437814442992584747365809754702131659640283734542679458996622865107315800
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_tl_intg_err/latest/run.log
  - 1.spi_device_tl_intg_err.111393842803417459058732190027537375541798766874971496912503653031899283519283
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_tl_intg_err/latest/run.log
  - ... and 18 more failures.
- Test spi_device_intr_test has 50 failures.
  - 0.spi_device_intr_test.24394061523694349432884129688732966049277481474294402798883643003427506134841
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_intr_test/latest/run.log
  - 1.spi_device_intr_test.1131160429658637341535146614507067827888900186007458563619591453191271298497
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_intr_test/latest/run.log
  - ... and 48 more failures.
- Test spi_device_mem_walk has 5 failures.
  - 0.spi_device_mem_walk.33650922923209902502307657850921721415190996594790358414174060015809500528064
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_mem_walk/latest/run.log
  - 1.spi_device_mem_walk.39318836102546929819954069359667128253114439523967583708242892989244097139816
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_mem_walk/latest/run.log
  - ... and 3 more failures.
- Test spi_device_mem_partial_access has 5 failures.
  - 0.spi_device_mem_partial_access.84840350211384723666598080394489329247165803919495434434562988319779906860456
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_mem_partial_access/latest/run.log
  - 1.spi_device_mem_partial_access.43358835026826236163111504404337466219581905455765554017681020689380197532763
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_mem_partial_access/latest/run.log
  - ... and 3 more failures.
- ... and 6 more tests.

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 2 failures:

Test spi_device_flash_and_tpm has 2 failures.

9.spi_device_flash_and_tpm.40264252374935484026367166804376834921008643309672119067635010753239128893295
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 8980988432 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_ERROR @ 8980988432 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadNotEmpty mismatch, act (0x0) != exp 1
  UVM_ERROR @ 8980988432 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare CmdFifoNotEmpty mismatch, act (0x0) != exp 1
  UVM_INFO @ 10761015008 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/15
  UVM_INFO @ 15787688344 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/15

23.spi_device_flash_and_tpm.69852376417806533915248088446664274191347798558600775373827085106871751437051
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 185702512 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 327609540 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/14
  UVM_INFO @ 483985840 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/20
  UVM_INFO @ 530516080 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/14
  UVM_INFO @ 842749995 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/20

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 2 failures:
- Test spi_device_flash_mode has 2 failures.
  - 11.spi_device_flash_mode.25522337205576050028194398739183520788843749240062794369881261447663747987067
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/11.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 113345066 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 2240342944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.spi_device_flash_mode.430392412390764837779028642172849193680843159564288642223951289212411354126
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/46.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 107440560 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 324353060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_stress_all has 2 failures.

24.spi_device_stress_all.69751091046364589328449427774267347053112945227403869565413412721498841409725
Line 274, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 4083568338 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 4160568261 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 1/3
  UVM_INFO @ 4161032907 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 2/3
  UVM_INFO @ 4161416745 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 3/3
  UVM_INFO @ 4171982391 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 1/3

34.spi_device_stress_all.84987753890061497589391305586688760056221061383138595189448781244240527554202
Line 274, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 6159563270 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 6246159791 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 1/6
  UVM_INFO @ 6246847313 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 2/6
  UVM_INFO @ 6247430665 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 3/6
  UVM_INFO @ 6248107770 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 4/6

Copying gs://7fa5dc6d-7dd3-3f84-9a7e-4f1238163bf8/EDAFarmArchive/tarballs/*/*/*/*/opentitan2_cluster:smart-b319f870-b7e7-4e02-af7f-17d79536f2ae/output.tar.gz... / [* files][ * B/ * MiB] Tracker file doesn't match for download of /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/cover_reg_top/output.tar.gz. Restarting download from scratch. OSError: No such file or directory. - has 1 failures:
- Test cover_reg_top has 1 failures.
  - cover_reg_top
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/cover_reg_top/build.log