SPI_DEVICE/1R1W Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	15.617m	143.089ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.470s	125.041us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.970s	231.709us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.170s	2.798ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.480s	1.163ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.810s	183.416us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.970s	231.709us	20	20	100.00
		spi_device_csr_aliasing	24.480s	1.163ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	14.260us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.170s	51.617us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	22.947us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	1.615us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	17.876us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	11.500s	6.437ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.500s	6.437ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	34.000s	40.156ms	50	50	100.00
		spi_device_tpm_sts_read	1.180s	187.343us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.496m	35.129ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	42.010s	62.227ms	50	50	100.00
		spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.350s	25.531ms	50	50	100.00
		spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.350s	25.531ms	50	50	100.00
		spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	cmd_info_slots	spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	cmd_read_status	spi_device_intercept	16.520s	4.784ms	50	50	100.00
		spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	cmd_read_jedec	spi_device_intercept	16.520s	4.784ms	50	50	100.00
		spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	cmd_read_sfdp	spi_device_intercept	16.520s	4.784ms	50	50	100.00
		spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	cmd_fast_read	spi_device_intercept	16.520s	4.784ms	50	50	100.00
		spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	cmd_read_pipeline	spi_device_intercept	16.520s	4.784ms	50	50	100.00
		spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	flash_cmd_upload	spi_device_upload	41.770s	51.453ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.062m	19.711ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.062m	19.711ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.062m	19.711ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.296m	60.285ms	48	50	96.00
		spi_device_read_buffer_direct	6.470s	3.055ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.062m	19.711ms	50	50	100.00
		spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	quad_spi	spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	dual_spi	spi_device_flash_all	6.293m	86.963ms	48	50	96.00
V2	4b_3b_feature	spi_device_cfg_cmd	13.090s	14.557ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	13.090s	14.557ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	15.617m	143.089ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.004m	411.866ms	47	50	94.00
V2	stress_all	spi_device_stress_all	19.869m	164.264ms	47	50	94.00
V2	alert_test	spi_device_alert_test	0.770s	54.691us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	33.973us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.000s	65.380us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.000s	65.380us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.470s	125.041us	5	5	100.00
		spi_device_csr_rw	2.970s	231.709us	20	20	100.00
		spi_device_csr_aliasing	24.480s	1.163ms	5	5	100.00
		spi_device_same_csr_outstanding	4.920s	898.414us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.470s	125.041us	5	5	100.00
		spi_device_csr_rw	2.970s	231.709us	20	20	100.00
		spi_device_csr_aliasing	24.480s	1.163ms	5	5	100.00
		spi_device_same_csr_outstanding	4.920s	898.414us	20	20	100.00
V2		TOTAL			950	980	96.94
V2S	tl_intg_err	spi_device_sec_cm	1.380s	1.076ms	5	5	100.00
		spi_device_tl_intg_err	27.060s	3.899ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	27.060s	3.899ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1090	1120	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	17	77.27
V2S	2	2	2	100.00
V3	1	0	0	0.00

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.74487545913868754687618163897413952634515835666941897928953553894027351844820
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2390279 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[102])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2390279 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2390279 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[998])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.114687533866536673058595311786487396814283393588241705336995223900749063044366
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1028010 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[63])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1028010 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1028010 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[959])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_flash_all has 2 failures.

2.spi_device_flash_all.23308967908834484783603666198949090363750288731037160532205468694902791985633
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 24023111194 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 24101676450 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 14/20
  UVM_INFO @ 25801801723 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 15/20
  UVM_INFO @ 26563523553 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 16/20
  UVM_INFO @ 27432044366 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 17/20

27.spi_device_flash_all.48671045246602754393840380182169584307861692923291575002626260445285873643862
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/27.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 2118164344 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 2184124344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_stress_all has 1 failures.

21.spi_device_stress_all.51157354167759750252646320272378719523487798489947854601737332491232888342096
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/21.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 6488502883 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 6635247883 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/19
  UVM_INFO @ 7118920883 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/19
  UVM_INFO @ 8109929883 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/19
  UVM_INFO @ 8907973883 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/19

Test spi_device_flash_and_tpm_min_idle has 1 failures.

40.spi_device_flash_and_tpm_min_idle.39978368419897799912774441135732090950399602059184941504959259774694050983069
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 4603349991 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 4767959425 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 14/16
  UVM_INFO @ 5077261572 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 15/16
  UVM_INFO @ 5343331843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_device_scoreboard.sv:891) [scoreboard] timeout occurred! has 2 failures:
- Test spi_device_flash_mode has 2 failures.
  - 47.spi_device_flash_mode.49694358754243351180420228843981814050570601067879762134915442309069664751954
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 89063017149 ps: (spi_device_scoreboard.sv:891) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 89063017149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.spi_device_flash_mode.53182076369749163643872826810978185815826766544418835578848971926838981117468
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 48668442169 ps: (spi_device_scoreboard.sv:891) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 48668442169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1024) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_stress_all has 1 failures.

0.spi_device_stress_all.50956565275810716732598295938569388479917604385110707551032667021546381265717
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 3846707754 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcd4608) != exp '{'{other_status:'h298b1a, wel:'h1, busy:'h0}}
  UVM_INFO @ 4080047589 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/14
  UVM_INFO @ 4289909935 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/14
  UVM_INFO @ 4652636697 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/14
  UVM_INFO @ 5136937551 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 13/14

UVM_ERROR (spi_device_scoreboard.sv:1024) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

6.spi_device_flash_and_tpm_min_idle.34565186397833287662946727852190295545687937881719844803390094023340909567792
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 368650659 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xde69aa) != exp '{'{other_status:'h4dea8, wel:'h0, busy:'h0}, '{other_status:'h18ca39, wel:'h0, busy:'h0}}
  UVM_INFO @ 368880659 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/3
  UVM_INFO @ 1116989659 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 1/18
  UVM_INFO @ 2404275659 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/18
  UVM_INFO @ 2780050659 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/3

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_stress_all has 1 failures.

23.spi_device_stress_all.103050639803711389359286730120945464762785956714827786440669690465970919209513
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 70190366899 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 70212440951 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/8
  UVM_INFO @ 75732435431 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 4/20
  UVM_INFO @ 107675207831 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/20
  UVM_INFO @ 118967577381 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/8

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_and_tpm_min_idle has 1 failures.
  - 44.spi_device_flash_and_tpm_min_idle.28901913614717681539031333094541669580704268281261514780799771902926936830704
    Line 270, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job spi_device-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": symlink /workspace/mnt/input/cov_merge /workspace/mnt/input/cov_merge: file exists has 1 failures:
- Test spi_device has 1 failures.
  - cov_report
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/cov_report/cov_report.log
```
  Job ID: smart:e4ae63d9-4a1a-477d-8ec7-86370dc3b457
```