1fbe1ece8d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 16.400s | 16.506ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.420s | 41.702us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.750s | 93.788us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 36.370s | 6.222ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 22.070s | 9.941ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 4.190s | 165.438us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.750s | 93.788us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 22.070s | 9.941ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.690s | 19.728us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 2.260s | 70.428us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.830s | 40.643us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.760s | 1.504us | 0 | 20 | 0.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.820s | 14.717us | 20 | 20 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 14.150s | 1.421ms | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 14.150s | 1.421ms | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 33.300s | 52.273ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.250s | 170.768us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.256m | 77.147ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 35.800s | 13.917ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 42.350s | 16.847ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 42.350s | 16.847ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 39.560s | 7.285ms | 41 | 50 | 82.00 |
| spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 39.560s | 7.285ms | 41 | 50 | 82.00 |
| spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 39.560s | 7.285ms | 41 | 50 | 82.00 |
| spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 39.560s | 7.285ms | 41 | 50 | 82.00 |
| spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 39.560s | 7.285ms | 41 | 50 | 82.00 |
| spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 51.940s | 16.866ms | 41 | 50 | 82.00 |
| V2 | mailbox_command | spi_device_mailbox | 2.438m | 56.430ms | 45 | 50 | 90.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 2.438m | 56.430ms | 45 | 50 | 90.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 2.438m | 56.430ms | 45 | 50 | 90.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 3.960m | 84.124ms | 41 | 50 | 82.00 |
| spi_device_read_buffer_direct | 21.580s | 1.749ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 2.438m | 56.430ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 20.250s | 4.616ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 30.270s | 3.999ms | 26 | 50 | 52.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 30.270s | 3.999ms | 26 | 50 | 52.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 16.400s | 16.506ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 33.080s | 6.188ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 4.950s | 272.563us | 10 | 50 | 20.00 |
| V2 | alert_test | spi_device_alert_test | 0.790s | 44.621us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.800s | 26.063us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 4.820s | 413.259us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 4.820s | 413.259us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.420s | 41.702us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.750s | 93.788us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 22.070s | 9.941ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.110s | 796.045us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.420s | 41.702us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.750s | 93.788us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 22.070s | 9.941ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.110s | 796.045us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 764 | 980 | 77.96 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.130s | 97.103us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 22.240s | 829.027us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 22.240s | 829.027us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 854 | 1120 | 76.25 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 13 | 59.09 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.00 | 97.49 | 92.77 | 98.61 | 80.85 | 95.83 | 90.96 | 87.49 |
Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 214 failures:
0.spi_device_intercept.54531949740833677177249762917314553761291360231709949228986134640186233522438
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest/run.log
Job ID: smart:164a3f48-6162-4372-9719-609703af8a74
6.spi_device_intercept.54005406055288119478898708498917543797833621592412386358353686847193073864631
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest/run.log
Job ID: smart:ec72ce71-d748-40e3-bd21-05ea89efb213
... and 7 more failures.
0.spi_device_flash_mode.105216181956507803605223502274220818200703321482043934278692655432194608632064
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest/run.log
Job ID: smart:7712de8d-52ac-4706-92a9-214971488ca9
5.spi_device_flash_mode.47632039529598485642427313313717020533755855645558536274896242492780050505590
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest/run.log
Job ID: smart:a7669b98-2a33-4a40-9e19-34407d1d967f
... and 6 more failures.
0.spi_device_flash_all.90527735866959085916676412204008440067379243354766950159307143887339489735476
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:89eed18e-5e07-4b37-b5b5-71e8763ee89d
1.spi_device_flash_all.11706364119812762845568552407568212718527881007030831446207504110814047618974
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:75011785-34fe-4b20-8be6-3d2e4b438c83
... and 40 more failures.
0.spi_device_flash_and_tpm.43043093816398774117695958101554101617793352781504310608605193926054210474029
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:f9aaedbf-2245-4587-9bc7-1ff0bdf703fa
1.spi_device_flash_and_tpm.39909518873098018758181193609018788552334004754749500048372503925026764355369
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:25f6fd67-beaf-46b7-ba52-cfe5c1f4e482
... and 44 more failures.
0.spi_device_flash_and_tpm_min_idle.62223246713836748521455910292763448757084659549035143367092307436480568263475
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:df8c7528-816f-4360-af59-3577aa59e811
1.spi_device_flash_and_tpm_min_idle.17132257115484962377039234344078246395506915999534329633678080007223211238233
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:180d0c58-875b-40e0-ae9c-133047805753
... and 44 more failures.
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
0.spi_device_mem_parity.87848532998811623831109959638977675500655875109591036796203266328162602167046
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 1248930 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[84])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1248930 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1248930 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[980])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.33172032484980001686813208309202836823993175148182785305431964040848610271531
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 1021423 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[108])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1021423 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1021423 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1004])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 13 failures:
Test spi_device_upload has 5 failures.
0.spi_device_upload.46083820816604986420364583528749924538875187441647685286387154649655756414958
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest/run.log
UVM_ERROR @ 2526504194 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 2536264923 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 2537071781 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0x3
UVM_INFO @ 2541473423 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0x41
UVM_ERROR @ 2547025684 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
23.spi_device_upload.82787697462920231091665510573759487509516140842207474254344820077347084829355
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest/run.log
UVM_ERROR @ 218052333 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 224671513 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 224707228 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 224707228 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
UVM_ERROR @ 234243133 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
... and 3 more failures.
Test spi_device_cfg_cmd has 3 failures.
9.spi_device_cfg_cmd.103053594262941494552431920726983891847550980083058282886676489548259166690020
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 591727611 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x83ae5a) != exp '{'{other_status:'h20eb96, wel:'h0, busy:'h0}, '{other_status:'h20eb96, wel:'h0, busy:'h0}}
UVM_ERROR @ 591892555 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x83ae5a) != exp '{'{other_status:'h20eb96, wel:'h0, busy:'h0}, '{other_status:'h20eb96, wel:'h0, busy:'h0}}
UVM_ERROR @ 596645004 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x83ae5a) != exp '{'{other_status:'h20eb96, wel:'h0, busy:'h0}, '{other_status:'h20eb96, wel:'h0, busy:'h0}}
UVM_INFO @ 601645004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.spi_device_cfg_cmd.98210977863586279257919910835010376063829758004474675685933139580371280340273
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 323941829 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x259482) != exp '{'{other_status:'h96520, wel:'h0, busy:'h0}, '{other_status:'h96520, wel:'h0, busy:'h0}}
UVM_ERROR @ 329799007 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x259482) != exp '{'{other_status:'h96520, wel:'h0, busy:'h0}, '{other_status:'h96520, wel:'h0, busy:'h0}}
UVM_INFO @ 331370445 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0xb7
UVM_ERROR @ 332084735 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x259482) != exp '{'{other_status:'h96520, wel:'h0, busy:'h0}, '{other_status:'h96520, wel:'h0, busy:'h0}}
UVM_ERROR @ 401442294 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x259482) != exp '{'{other_status:'h96520, wel:'h0, busy:'h0}, '{other_status:'h96520, wel:'h0, busy:'h0}}
... and 1 more failures.
Test spi_device_flash_all has 2 failures.
18.spi_device_flash_all.21854250990938541654400554255860439056346705003303138535115869021470381195598
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest/run.log
UVM_ERROR @ 533081720 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 2378448046 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2378448046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_device_flash_all.110636811680400802488266958101985595515053832824763272417294089465959789514668
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest/run.log
UVM_ERROR @ 2654978461 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xd26a6) != exp '{'{other_status:'h349a9, wel:'h0, busy:'h0}, '{other_status:'h349a9, wel:'h0, busy:'h0}}
UVM_ERROR @ 2811580027 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xd26a6) != exp '{'{other_status:'h349a9, wel:'h0, busy:'h0}, '{other_status:'h349a9, wel:'h0, busy:'h0}}
UVM_ERROR @ 3782389735 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h1e0840, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 3782971559 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h1e0840, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 3783553383 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h1e0840, wel:'h0, busy:'h0}} ) pred=0x0
Test spi_device_stress_all has 1 failures.
38.spi_device_stress_all.85205464352506257636826807829448533267606344933259735227086101700142614287913
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest/run.log
UVM_ERROR @ 259419318 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 272562807 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 272562807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm_min_idle has 1 failures.
39.spi_device_flash_and_tpm_min_idle.82319550774007524422036286445138086977822803551598734135729939244118482813070
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 268874324 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3c6195) != exp '{'{other_status:'hf1865, wel:'h0, busy:'h0}, '{other_status:'hf1865, wel:'h0, busy:'h0}}
UVM_FATAL @ 306380325 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 306380325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 13 failures:
Test spi_device_upload has 4 failures.
3.spi_device_upload.66112365674901870911461326233226044680292057615848094475228538713542513547089
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest/run.log
UVM_FATAL @ 1088669793 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1088669793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_device_upload.19708028018697229774470001263937204485502452070679530048133670176365961133919
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest/run.log
UVM_FATAL @ 754581659 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 754581659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_flash_all has 6 failures.
4.spi_device_flash_all.98889232903440102572791522093000567382168331777605045744522492064448237855746
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest/run.log
UVM_FATAL @ 60646250 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 60646250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_device_flash_all.110394876316750553871696119303170072028177748572211182540517749476182236321302
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest/run.log
UVM_FATAL @ 4616144070 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4616144070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_device_stress_all has 1 failures.
24.spi_device_stress_all.111857614678897485839539664790060602188629674564548524700783528044533670779375
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest/run.log
UVM_FATAL @ 116481695 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 116481695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm_min_idle has 2 failures.
43.spi_device_flash_and_tpm_min_idle.62533631325782606482829126254444185966898981538769303740899545525630816253703
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 176487904 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 176487904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.spi_device_flash_and_tpm_min_idle.68522184272652123526542748841906196668629872925090517558917578969735960537371
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 2954107391 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2954107391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 5 failures:
Test spi_device_flash_and_tpm has 3 failures.
25.spi_device_flash_and_tpm.30452569855166970119708881496041927427134403822745335582373263609772900761280
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 46228621 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1bd4b8, wel:'h0, busy:'h0}}
UVM_FATAL @ 152714622 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 152714622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.spi_device_flash_and_tpm.58888712426609881573142453161065619994704641031929940807063345378238907340463
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 146047891 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1fc614, wel:'h0, busy:'h0}}
UVM_INFO @ 217609246 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/6
UVM_FATAL @ 260502187 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 260502187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_device_flash_and_tpm_min_idle has 1 failures.
36.spi_device_flash_and_tpm_min_idle.33559437665880224244204520491614728321781516400775724968177676292588262129648
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 6102159550 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1460ba) != exp '{'{other_status:'h5182e, wel:'h0, busy:'h0}, '{other_status:'h5182e, wel:'h0, busy:'h0}, '{other_status:'h161191, wel:'h0, busy:'h0}}
UVM_ERROR @ 6141920550 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h161191, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 6142880550 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h161191, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 6143840550 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h161191, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 6144800550 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h161191, wel:'h0, busy:'h0}} ) pred=0x0
Test spi_device_cfg_cmd has 1 failures.
45.spi_device_cfg_cmd.54649957897361561616938200753424032093989066423838046391332768827479044301598
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 208196548 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h146f46, wel:'h0, busy:'h0}}
UVM_ERROR @ 209396548 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h146f46, wel:'h0, busy:'h0}}
UVM_ERROR @ 210396548 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h146f46, wel:'h0, busy:'h0}}
UVM_ERROR @ 210796548 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h146f46, wel:'h0, busy:'h0}, '{other_status:'h146f46, wel:'h0, busy:'h0}}
UVM_ERROR @ 212596548 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x51bd1a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h146f46, wel:'h0, busy:'h0}, '{other_status:'h146f46, wel:'h0, busy:'h0}}
UVM_FATAL (spi_device_scoreboard.sv:1124) [scoreboard] timeout occurred! has 1 failures:
44.spi_device_flash_mode.104976646342761384841668682362019285712967217018443007951772302797162340623584
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest/run.log
UVM_FATAL @ 45256807830 ps: (spi_device_scoreboard.sv:1124) [uvm_test_top.env.scoreboard] timeout occurred!
UVM_INFO @ 45256807830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---