9f4903e77a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 12.490s | 5.790ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.410s | 182.775us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 3.010s | 1.517ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 37.450s | 1.891ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 22.190s | 324.068us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 4.180s | 238.599us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 3.010s | 1.517ms | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 22.190s | 324.068us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.660s | 34.164us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.880s | 86.650us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.890s | 16.832us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.730s | 4.327us | 0 | 20 | 0.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.760s | 18.330us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 10.120s | 558.679us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 10.120s | 558.679us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 31.790s | 10.758ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.290s | 197.330us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.227m | 51.591ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 36.630s | 26.618ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 50.180s | 19.120ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 50.180s | 19.120ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 36.920s | 3.480ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 36.920s | 3.480ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 36.920s | 3.480ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 36.920s | 3.480ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 36.920s | 3.480ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 56.490s | 71.274ms | 37 | 50 | 74.00 |
| V2 | mailbox_command | spi_device_mailbox | 1.906m | 39.006ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 1.906m | 39.006ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 1.906m | 39.006ms | 46 | 50 | 92.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 2.661m | 11.952ms | 41 | 50 | 82.00 |
| spi_device_read_buffer_direct | 19.520s | 1.792ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 1.906m | 39.006ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 24.860s | 12.169ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 29.650s | 29.419ms | 24 | 50 | 48.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 29.650s | 29.419ms | 24 | 50 | 48.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 12.490s | 5.790ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 10.730s | 8.572ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 1.204m | 7.174ms | 12 | 50 | 24.00 |
| V2 | alert_test | spi_device_alert_test | 0.800s | 23.304us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.810s | 14.821us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 4.970s | 689.602us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 4.970s | 689.602us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.410s | 182.775us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 3.010s | 1.517ms | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 22.190s | 324.068us | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.540s | 745.370us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.410s | 182.775us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 3.010s | 1.517ms | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 22.190s | 324.068us | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.540s | 745.370us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 744 | 961 | 77.42 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.160s | 213.418us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 24.050s | 6.324ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 24.050s | 6.324ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 834 | 1101 | 75.75 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 13 | 59.09 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.04 | 97.49 | 92.82 | 98.61 | 80.85 | 95.85 | 90.96 | 87.69 |
Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 207 failures:
0.spi_device_cfg_cmd.8288109899401715826141601349788154947644764817107087549516860378630169256720
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
Job ID: smart:ab165762-5ab4-44bb-89ae-09658fe8ca91
1.spi_device_cfg_cmd.57872710110615395458274784045519660955282328853854918137267240696256779922679
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
Job ID: smart:511d790f-ebb6-4087-bd9e-8d2790b00d80
... and 18 more failures.
0.spi_device_flash_all.22595745148995474975966622933736736017075377059410154989336800144700340104923
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:80a4ad19-4dbf-472f-971c-455a63fabd46
2.spi_device_flash_all.113864549882098396008305132477588258849120360349392750568432059344562308156968
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest/run.log
Job ID: smart:40b3a4d6-4b9f-4227-9bbd-46e77b338aa1
... and 45 more failures.
0.spi_device_flash_and_tpm.70010647357734037460084305413915724888481111031685144911850463189358717845394
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:846f584c-fa55-4922-924a-07be64895a37
1.spi_device_flash_and_tpm.74268667754625349725228391849515055662323593998167165631173795361624429651749
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:b5d18524-106a-4a45-800c-6d6366aa1f0a
... and 43 more failures.
0.spi_device_flash_and_tpm_min_idle.61655062092029959442320466122897728543847529966742090011281291259404831570172
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:7f2dc60c-abe2-4e58-a851-7b1bab0d4a15
1.spi_device_flash_and_tpm_min_idle.6922046101702309610514249026049825482978940765884804201737401675113223497160
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:c20a4129-9592-4d13-b9b7-31898bbe09f4
... and 42 more failures.
0.spi_device_stress_all.67087524804780410631772353154410919453978823142124739579550546865909251751106
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest/run.log
Job ID: smart:10c33df1-7a8f-47b9-8a58-eb24c47d2674
1.spi_device_stress_all.76281944440240829831220452540710857834277580631803792429917485372632309675513
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest/run.log
Job ID: smart:33495589-844b-4df9-8dc5-c999d47ebda5
... and 29 more failures.
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
0.spi_device_mem_parity.38706431384665044643919431801062335831679614433259329565128699546530885864856
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 3287885 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[96])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3287885 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3287885 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[992])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.103911270725018519756578174313491770669771915558611377206456303228164946534779
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 4849617 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[101])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 4849617 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 4849617 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[997])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 20 failures:
Test spi_device_upload has 8 failures.
0.spi_device_upload.68312283145266201314475986020471215865053321297310690450243784931152885757918
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest/run.log
UVM_ERROR @ 25532980063 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 25808381440 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 25817632818 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0x24
UVM_INFO @ 30199336728 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0xfd
UVM_INFO @ 31301896573 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 7, test op = 0xb
1.spi_device_upload.58371554659129777966768090048220191788578460306612395631502968059587429229129
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest/run.log
UVM_ERROR @ 26110157158 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 26128323534 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 26133125359 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 16, test op = 0xb0
UVM_INFO @ 29615577886 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 17, test op = 0x15
UVM_INFO @ 29625801294 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 18, test op = 0x43
... and 6 more failures.
Test spi_device_flash_all has 1 failures.
1.spi_device_flash_all.61073021004825061206647638161189600310284643922243589055948343947497770579470
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
UVM_ERROR @ 41479851 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 53119851 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 221239851 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xbd1062) != exp '{'{other_status:'h2f4418, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2f4418, wel:'h0, busy:'h0}, '{other_status:'h2f4418, wel:'h0, busy:'h0}}
UVM_ERROR @ 221559851 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h2f4418, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 221719851 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h2f4418, wel:'h0, busy:'h0}} ) pred=0x0
Test spi_device_flash_and_tpm has 2 failures.
13.spi_device_flash_and_tpm.115545203720076581040074729911165315911704722689026736480541067470724519450769
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 480053861 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 513755092 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 513755092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_device_flash_and_tpm.12755653064605396076932016556514553925624677735358123217929829360869307994755
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 836619836 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xfc79b5) != exp '{'{other_status:'h3f1e6d, wel:'h0, busy:'h0}, '{other_status:'h3f1e6d, wel:'h0, busy:'h0}}
UVM_FATAL @ 837396757 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 837396757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_cfg_cmd has 4 failures.
19.spi_device_cfg_cmd.69453044126450001670252813444725158031633537952502135527641144589503661402053
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 666049498 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa3bfd6) != exp '{'{other_status:'h28eff5, wel:'h0, busy:'h0}, '{other_status:'h28eff5, wel:'h0, busy:'h0}}
UVM_ERROR @ 666417908 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa3bfd6) != exp '{'{other_status:'h28eff5, wel:'h0, busy:'h0}, '{other_status:'h28eff5, wel:'h0, busy:'h0}}
UVM_ERROR @ 666754740 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa3bfd6) != exp '{'{other_status:'h28eff5, wel:'h0, busy:'h0}, '{other_status:'h28eff5, wel:'h0, busy:'h0}}
UVM_INFO @ 666965260 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 10, test op = 0x6
UVM_ERROR @ 667207358 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa3bfd6) != exp '{'{other_status:'h28eff5, wel:'h0, busy:'h0}, '{other_status:'h28eff5, wel:'h0, busy:'h0}}
35.spi_device_cfg_cmd.6467715499572145471700387282408856436419398728072490283495467381801618921936
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 59787750 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xef21d6) != exp '{'{other_status:'h3bc875, wel:'h0, busy:'h0}, '{other_status:'h3bc875, wel:'h0, busy:'h0}}
UVM_ERROR @ 60685702 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xef21d6) != exp '{'{other_status:'h3bc875, wel:'h0, busy:'h0}, '{other_status:'h3bc875, wel:'h0, busy:'h0}}
UVM_INFO @ 61440798 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 5, test op = 0xe9
UVM_ERROR @ 61787734 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xef21d6) != exp '{'{other_status:'h3bc875, wel:'h0, busy:'h0}, '{other_status:'h3bc875, wel:'h0, busy:'h0}}
UVM_ERROR @ 110481222 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xef21d6) != exp '{'{other_status:'h3bc875, wel:'h0, busy:'h0}, '{other_status:'h3bc875, wel:'h0, busy:'h0}}
... and 2 more failures.
Test spi_device_flash_and_tpm_min_idle has 3 failures.
19.spi_device_flash_and_tpm_min_idle.72862304724230483548635288448906276901778553916826151513937875123350819139037
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 80871053 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 91349046 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 91349046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_device_flash_and_tpm_min_idle.65091253493990651579885262953133559656644978337216880268304199056936846618362
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 8552822524 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 8572462399 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 8572462399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
... and 1 more tests.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 16 failures:
Test spi_device_upload has 5 failures.
6.spi_device_upload.111134628746631300473599406112959339608893928911812151644819504367001116677442
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest/run.log
UVM_FATAL @ 1031029216 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1031029216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_device_upload.95495325728927926662942773236937312321018942820354947873591844004406484038950
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest/run.log
UVM_FATAL @ 603128275 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 603128275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_device_stress_all has 4 failures.
9.spi_device_stress_all.104618072371979961530284614870312074441567639220958687228127089564623910143844
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest/run.log
UVM_FATAL @ 427414404 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 427414404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_device_stress_all.65928502613377297633981076660329453408869385798281893734306395018308713457924
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest/run.log
UVM_FATAL @ 7174464928 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7174464928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_flash_all has 2 failures.
19.spi_device_flash_all.74230908674965511231404758369915399310455767828487939244748552084612672693969
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest/run.log
UVM_FATAL @ 8108126861 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 8108126861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_device_flash_all.15674419731514727994570953457871093597524086777563266164502764170468232104007
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest/run.log
UVM_FATAL @ 12169371434 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12169371434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 3 failures.
24.spi_device_flash_and_tpm.16278627797134948448389520557827554676893484698632239524127288582382527505360
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 5790380672 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5790380672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_device_flash_and_tpm.79724614863796239583361895622021657988752683587717869827978101240837276476514
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 570721412 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 570721412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_device_flash_and_tpm_min_idle has 2 failures.
24.spi_device_flash_and_tpm_min_idle.618118994148617062205973054657219080173783616395304499061546149524187884479
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 439249688 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 439249688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_device_flash_and_tpm_min_idle.51722648364049851783221926722502104421184435847616668669681372453500486077627
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 153271167 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 153271167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 3 failures:
Test spi_device_cfg_cmd has 2 failures.
24.spi_device_cfg_cmd.113807403264741365647551848844535793743775614655157663872847481357988637669684
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 167859057 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x7f642e) != exp '{'{other_status:'ha4812, wel:'h0, busy:'h0}, '{other_status:'h1fd90b, wel:'h0, busy:'h0}, '{other_status:'h1fd90b, wel:'h0, busy:'h0}}
UVM_ERROR @ 169359069 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x7f642e) != exp '{'{other_status:'ha4812, wel:'h0, busy:'h0}, '{other_status:'h1fd90b, wel:'h0, busy:'h0}, '{other_status:'h1fd90b, wel:'h0, busy:'h0}}
UVM_ERROR @ 171650754 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x7f642e) != exp '{'{other_status:'ha4812, wel:'h0, busy:'h0}, '{other_status:'h1fd90b, wel:'h0, busy:'h0}, '{other_status:'h1fd90b, wel:'h0, busy:'h0}}
UVM_ERROR @ 173817438 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x7f642e) != exp '{'{other_status:'h1fd90b, wel:'h0, busy:'h0}, '{other_status:'ha4812, wel:'h0, busy:'h0}, '{other_status:'h1fd90b, wel:'h0, busy:'h0}, '{other_status:'h1fd90b, wel:'h0, busy:'h0}}
UVM_ERROR @ 174942447 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x7f642e) != exp '{'{other_status:'h1fd90b, wel:'h0, busy:'h0}, '{other_status:'ha4812, wel:'h0, busy:'h0}, '{other_status:'h1fd90b, wel:'h0, busy:'h0}, '{other_status:'h1fd90b, wel:'h0, busy:'h0}}
49.spi_device_cfg_cmd.813603338463911014747913137944742290054333822645521568609723114674083895851
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 47187038 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x4fe62a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h13f98a, wel:'h0, busy:'h0}, '{other_status:'h13f98a, wel:'h0, busy:'h0}}
UVM_ERROR @ 48034859 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x4fe62a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h13f98a, wel:'h0, busy:'h0}, '{other_status:'h13f98a, wel:'h0, busy:'h0}}
UVM_ERROR @ 48339205 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x4fe62a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h13f98a, wel:'h0, busy:'h0}, '{other_status:'h13f98a, wel:'h0, busy:'h0}}
UVM_ERROR @ 48708768 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x4fe62a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h13f98a, wel:'h0, busy:'h0}, '{other_status:'h13f98a, wel:'h0, busy:'h0}}
UVM_ERROR @ 49513111 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x4fe62a) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h13f98a, wel:'h0, busy:'h0}, '{other_status:'h13f98a, wel:'h0, busy:'h0}, '{other_status:'h3753cd, wel:'h0, busy:'h0}}
Test spi_device_stress_all has 1 failures.
35.spi_device_stress_all.58817341485433985301515759610289068054656131233129605467792164251579167884592
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest/run.log
UVM_ERROR @ 587309464 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h113232, wel:'h0, busy:'h0}}
UVM_INFO @ 904802653 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/8
UVM_ERROR @ 1246088026 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x44c8ca) != exp '{'{other_status:'h113232, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h113232, wel:'h0, busy:'h0}, '{other_status:'h113232, wel:'h0, busy:'h0}}
UVM_FATAL @ 1464078055 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1464078055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (spi_device_scoreboard.sv:969) scoreboard [scoreboard] WEL mismatch: act=*, pred_fuzzy_q ('{'{other_status:*, wel:*, busy:*}} ) pred=* has 1 failures:
28.spi_device_flash_and_tpm_min_idle.90724416639257769488713096994858838736086902331801047234736957726299221346678
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 1236589892 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3f1551, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 1240856580 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3f1551, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 1245123268 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3f1551, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 1249389956 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3f1551, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 1253656644 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3f1551, wel:'h0, busy:'h0}} ) pred=0x0