SPI_DEVICE/1R1W Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	19.600s	2.769ms	0	50	0.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.430s	41.464us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.680s	38.386us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.390s	5.385ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.110s	1.045ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.870s	110.356us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.680s	38.386us	20	20	100.00
		spi_device_csr_aliasing	16.110s	1.045ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	37.505us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.390s	76.084us	5	5	100.00
V1		TOTAL			65	115	56.52
V2	csb_read	spi_device_csb_read	0.850s	41.020us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	1.788us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	42.771us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	15.010s	356.517us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	15.010s	356.517us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	33.080s	51.426ms	50	50	100.00
		spi_device_tpm_sts_read	1.280s	218.261us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.218m	58.677ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	59.790s	20.973ms	50	50	100.00
		spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	39.500s	14.514ms	50	50	100.00
		spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	39.500s	14.514ms	50	50	100.00
		spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	cmd_info_slots	spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	cmd_read_status	spi_device_intercept	50.380s	4.803ms	46	50	92.00
		spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	cmd_read_jedec	spi_device_intercept	50.380s	4.803ms	46	50	92.00
		spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	cmd_read_sfdp	spi_device_intercept	50.380s	4.803ms	46	50	92.00
		spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	cmd_fast_read	spi_device_intercept	50.380s	4.803ms	46	50	92.00
		spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	cmd_read_pipeline	spi_device_intercept	50.380s	4.803ms	46	50	92.00
		spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	flash_cmd_upload	spi_device_upload	44.250s	33.771ms	40	50	80.00
V2	mailbox_command	spi_device_mailbox	3.739m	112.498ms	42	50	84.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.739m	112.498ms	42	50	84.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.739m	112.498ms	42	50	84.00
V2	cmd_read_buffer	spi_device_flash_mode	3.151m	14.920ms	41	50	82.00
		spi_device_read_buffer_direct	19.200s	5.061ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.739m	112.498ms	42	50	84.00
		spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	quad_spi	spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	dual_spi	spi_device_flash_all	1.097m	136.994ms	0	50	0.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.830s	10.268ms	22	50	44.00
V2	write_enable_disable	spi_device_cfg_cmd	27.830s	10.268ms	22	50	44.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	19.600s	2.769ms	0	50	0.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	49.430s	6.834ms	1	50	2.00
V2	stress_all	spi_device_stress_all	31.930s	18.920ms	11	50	22.00
V2	alert_test	spi_device_alert_test	0.780s	47.873us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.780s	16.556us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.570s	156.791us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.570s	156.791us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.430s	41.464us	5	5	100.00
		spi_device_csr_rw	2.680s	38.386us	20	20	100.00
		spi_device_csr_aliasing	16.110s	1.045ms	5	5	100.00
		spi_device_same_csr_outstanding	4.480s	340.987us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.430s	41.464us	5	5	100.00
		spi_device_csr_rw	2.680s	38.386us	20	20	100.00
		spi_device_csr_aliasing	16.110s	1.045ms	5	5	100.00
		spi_device_same_csr_outstanding	4.480s	340.987us	20	20	100.00
V2		TOTAL			744	961	77.42
V2S	tl_intg_err	spi_device_sec_cm	1.210s	211.250us	5	5	100.00
		spi_device_tl_intg_err	23.050s	1.593ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.050s	1.593ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			834	1101	75.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	13	59.09
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.15	97.51	92.84	98.61	80.85	95.88	90.96	88.38

Failure Buckets

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 212 failures:
- Test spi_device_cfg_cmd has 25 failures.
  - 0.spi_device_cfg_cmd.108451142008267612443652678075684329638411955903905870032900988877417357313570
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
```
  Job ID: smart:ed00145f-1a08-48f1-9b9b-e5458d4da7f3
```
  - 1.spi_device_cfg_cmd.95974376689036294678854593345270414013914292495034639035716909809123416594950
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
```
  Job ID: smart:0181fb88-c26c-4b48-805c-4f9ad11e9178
```
  - ... and 23 more failures.
- Test spi_device_flash_mode has 9 failures.
  - 0.spi_device_flash_mode.64587159185895730277202447361268338643991298991569621120803758824028375952554
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest/run.log
```
  Job ID: smart:13fed644-7e96-47fd-a1d6-443d56ae8160
```
  - 4.spi_device_flash_mode.60537696373234422756567715751900641220677967365722420011592869546195393738416
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest/run.log
```
  Job ID: smart:8239fa86-94e4-410d-89ce-b26bd7c38d3a
```
  - ... and 7 more failures.
- Test spi_device_flash_and_tpm has 46 failures.
  - 0.spi_device_flash_and_tpm.101039067650785496781277233187777455973053452202174618629142705940031744238905
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:740776f2-1978-4c1d-92d6-cc8ae493fc32
```
  - 1.spi_device_flash_and_tpm.50641401130495500809702118066768129592968527493595043023392110424886214583602
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:fb8b1872-97c4-49d3-a0a9-1fb6b2ba3c4f
```
  - ... and 44 more failures.
- Test spi_device_flash_and_tpm_min_idle has 49 failures.
  - 0.spi_device_flash_and_tpm_min_idle.95299992841239986159415513173706333267265368690074207341194112099933682519554
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:915f4352-9d87-41ee-ae2d-e5d5d1a48187
```
  - 1.spi_device_flash_and_tpm_min_idle.102794098762665114792981481698364872843872064085470028477384647212854308488336
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:3d0023a2-4a2e-4d9d-86dc-0bbe84f10399
```
  - ... and 47 more failures.
- Test spi_device_stress_all has 30 failures.
  - 0.spi_device_stress_all.75357200772838812702328366783851176655917082158927748389409007798018222099246
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest/run.log
```
  Job ID: smart:5842f827-8dde-40a4-bbb6-5c491e1ee4f8
```
  - 2.spi_device_stress_all.31741674300581182689715108694557343416770704318194074472194104510393448995690
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest/run.log
```
  Job ID: smart:d95060a3-4edd-45ec-a015-f96e613480c3
```
  - ... and 28 more failures.
- ... and 3 more tests.

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.37585806822376740156122591295981395118545131468016214029116396320536285683661
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2980788 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[58])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2980788 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2980788 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[954])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.114543064066878038764724591991505095706750854099834628360793797207678850987028
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1035610 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[95])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1035610 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1035610 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[991])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 19 failures:

Test spi_device_flash_all has 6 failures.

0.spi_device_flash_all.58361489435920296085249088473887239322910026441107956448501825964819378071404
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log

  UVM_FATAL @  98762826 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  98762826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.spi_device_flash_all.36516794735418719022307301838501106875950402023242778557212155181250759829416
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest/run.log

  UVM_FATAL @  95613811 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  95613811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test spi_device_stress_all has 7 failures.

1.spi_device_stress_all.32514519772989899929126642279509433970315308602919965939180993595618844524725
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest/run.log

  UVM_FATAL @ 10025393809 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 10025393809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.spi_device_stress_all.4715420738891759838956364896890508708427831508493490873313955785101236323825
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest/run.log

  UVM_FATAL @ 280849975 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 280849975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test spi_device_flash_and_tpm has 3 failures.

9.spi_device_flash_and_tpm.33245789586799623035473577722813053498739266394870882432154467092118060666312
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest/run.log

  UVM_FATAL @ 2769496088 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2769496088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.spi_device_flash_and_tpm.79264992394544239850371001660969579258732083583431862460132559468142857046414
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest/run.log

  UVM_FATAL @ 102324917 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 102324917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test spi_device_upload has 3 failures.

12.spi_device_upload.23365974702272710848900915962846702378712051451344792139140412148904121110557
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest/run.log

  UVM_FATAL @ 4838205903 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4838205903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.spi_device_upload.88487065197141425935074919895244746665280054859947022697758021881449109433193
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest/run.log

  UVM_FATAL @  48006817 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  48006817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 15 failures:

Test spi_device_upload has 7 failures.

2.spi_device_upload.25727010856145389926927593360603394455396982602347149483919867882282816558240
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest/run.log

  UVM_ERROR @ 167097746 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 173910464 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 176063115 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0x15
  UVM_INFO @ 305298749 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x15
  UVM_INFO @ 562540981 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0xe

8.spi_device_upload.102365329343637843665355277987954715266264725330368427952235820530851322638957
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest/run.log

  UVM_ERROR @ 818961864 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 826771864 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 829353864 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0x4f
  UVM_INFO @ 1322230864 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 7, test op = 0x47
  UVM_INFO @ 2723232864 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 8, test op = 0x56

... and 5 more failures.

Test spi_device_cfg_cmd has 3 failures.

3.spi_device_cfg_cmd.75272748055270306759182986443308476236265542899621076539901003252719396956143
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 1912514891 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1918514891 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 1923914891 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0xe9
  UVM_ERROR @ 1925714891 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1928914891 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}

5.spi_device_cfg_cmd.12491588164765232299749603806112661844616636677379281147481785490384954560037
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 198440492 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 199523808 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 199836303 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 200065466 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 200294629 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}

... and 1 more failures.

Test spi_device_flash_all has 2 failures.

7.spi_device_flash_all.11367647915260503935760391107203376639754101734314429109533236043128153497717
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 107687864469 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x933732) != exp '{'{other_status:'h24cdcc, wel:'h0, busy:'h0}, '{other_status:'h24cdcc, wel:'h0, busy:'h0}}
  UVM_ERROR @ 114398711224 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x933732) != exp '{'{other_status:'h24cdcc, wel:'h0, busy:'h0}, '{other_status:'h24cdcc, wel:'h0, busy:'h0}}
  UVM_ERROR @ 120922057604 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x933732) != exp '{'{other_status:'h24cdcc, wel:'h0, busy:'h0}, '{other_status:'h24cdcc, wel:'h0, busy:'h0}}
  UVM_ERROR @ 121669559099 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x933732) != exp '{'{other_status:'h24cdcc, wel:'h0, busy:'h0}, '{other_status:'h24cdcc, wel:'h0, busy:'h0}, '{other_status:'h8a1d5, wel:'h0, busy:'h0}}
  UVM_FATAL @ 136994089749 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])

49.spi_device_flash_all.39734441343767504808995615900974674806163832116836513407814332145241331039253
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 232187893 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe31bed) != exp '{'{other_status:'h38c6fb, wel:'h0, busy:'h0}, '{other_status:'h38c6fb, wel:'h0, busy:'h0}}
  UVM_ERROR @ 250381625 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe31bee) != exp '{'{other_status:'h38c6fb, wel:'h0, busy:'h0}, '{other_status:'h38c6fb, wel:'h0, busy:'h0}}
  UVM_INFO @ 255391829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_stress_all has 2 failures.

26.spi_device_stress_all.115342150404065246742976706743494433270677444939470331098252591880451279891713
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 120117473 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 228204265 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/10
  UVM_ERROR @ 380573724 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x4d76fd) != exp '{'{other_status:'h135dbf, wel:'h0, busy:'h0}, '{other_status:'h135dbf, wel:'h0, busy:'h0}}
  UVM_ERROR @ 502160948 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8e1b6) != exp '{'{other_status:'h2386d, wel:'h0, busy:'h0}, '{other_status:'h2386d, wel:'h0, busy:'h0}}
  UVM_ERROR @ 572871544 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8e1b6) != exp '{'{other_status:'h2386d, wel:'h0, busy:'h0}, '{other_status:'h2386d, wel:'h0, busy:'h0}}

45.spi_device_stress_all.84222190459668149002463393405128818298929154181573712498631914934837440070376
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 1630627743 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 18739333807 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h916e8, wel:'h0, busy:'h0}} ) pred=0x0
  UVM_ERROR @ 18743098543 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h916e8, wel:'h0, busy:'h0}} ) pred=0x0
  UVM_ERROR @ 18746863279 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h916e8, wel:'h0, busy:'h0}} ) pred=0x0
  UVM_ERROR @ 18750628015 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h916e8, wel:'h0, busy:'h0}} ) pred=0x0

Test spi_device_flash_and_tpm has 1 failures.

44.spi_device_flash_and_tpm.66039692040882159608868420491345456096469875763660203069600813373220054965095
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 850408831 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x35645) != exp '{'{other_status:'hd591, wel:'h0, busy:'h0}, '{other_status:'hd591, wel:'h0, busy:'h0}}
  UVM_FATAL @ 880327258 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 880327258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_all has 1 failures.

40.spi_device_flash_all.95081281989452773123734329575574839620672509767257186992492848195862741257866
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 690872402 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3ee8d3, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1865871604 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
  UVM_ERROR @ 1866201492 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
  UVM_ERROR @ 1869335428 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xfba34e) != exp '{'{other_status:'h3ee8d3, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3ee8d3, wel:'h0, busy:'h0}, '{other_status:'h3ee8d3, wel:'h0, busy:'h0}}
  UVM_ERROR @ 2005135885 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0