d3942ca074| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 1.019m | 5.214ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.480s | 180.284us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.770s | 117.911us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 33.290s | 8.688ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 24.180s | 1.265ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.960s | 135.320us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.770s | 117.911us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 24.180s | 1.265ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.710s | 26.468us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 2.090s | 227.536us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.860s | 20.822us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.740s | 1.255us | 0 | 20 | 0.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.810s | 17.074us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 6.430s | 121.375us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 6.430s | 121.375us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 33.180s | 54.603ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.160s | 514.218us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.298m | 13.826ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 37.350s | 12.124ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 51.910s | 39.136ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 51.910s | 39.136ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 46.080s | 8.870ms | 40 | 50 | 80.00 |
| spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 46.080s | 8.870ms | 40 | 50 | 80.00 |
| spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 46.080s | 8.870ms | 40 | 50 | 80.00 |
| spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 46.080s | 8.870ms | 40 | 50 | 80.00 |
| spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 46.080s | 8.870ms | 40 | 50 | 80.00 |
| spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 52.080s | 33.651ms | 33 | 50 | 66.00 |
| V2 | mailbox_command | spi_device_mailbox | 4.452m | 114.308ms | 47 | 50 | 94.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 4.452m | 114.308ms | 47 | 50 | 94.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 4.452m | 114.308ms | 47 | 50 | 94.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 3.357m | 64.372ms | 42 | 50 | 84.00 |
| spi_device_read_buffer_direct | 24.400s | 2.376ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 4.452m | 114.308ms | 47 | 50 | 94.00 |
| spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 11.630s | 742.881us | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 44.150s | 7.026ms | 21 | 50 | 42.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 44.150s | 7.026ms | 21 | 50 | 42.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 1.019m | 5.214ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 41.360s | 5.255ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 1.865m | 21.000ms | 10 | 50 | 20.00 |
| V2 | alert_test | spi_device_alert_test | 0.790s | 66.414us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.820s | 30.987us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.350s | 2.830ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 5.350s | 2.830ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.480s | 180.284us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.770s | 117.911us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 24.180s | 1.265ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.520s | 160.456us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.480s | 180.284us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.770s | 117.911us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 24.180s | 1.265ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.520s | 160.456us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 734 | 961 | 76.38 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.250s | 392.560us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 22.880s | 1.026ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 22.880s | 1.026ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 824 | 1101 | 74.84 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 13 | 59.09 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.10 | 97.49 | 92.80 | 98.61 | 80.85 | 95.83 | 90.96 | 88.18 |
Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 207 failures:
0.spi_device_intercept.71991775251388370915891160485207613960135123893598730549308036138043118474957
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest/run.log
Job ID: smart:4a0ac9d1-4592-4291-a30b-1907256acc16
3.spi_device_intercept.107046324876692443245144578958969412350897036380204816262761038170053181175713
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest/run.log
Job ID: smart:3579f5f3-9d3f-430d-a0eb-908b30018d19
... and 8 more failures.
0.spi_device_cfg_cmd.24772755208843074627649283455420049048427891074105422218593608899197841095014
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
Job ID: smart:f6888eba-e372-4d52-8bdf-4f7d09fb14e1
5.spi_device_cfg_cmd.108161684776400131391498590490308545814136896704637000680106722260410653181529
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest/run.log
Job ID: smart:56a54e31-64cc-4d91-8657-884cd55db66a
... and 15 more failures.
0.spi_device_flash_all.53241156712596724444700186805679713951457249021171539341997531684169848546445
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:fddffc71-cb8a-4d61-aafd-8b348c00be88
1.spi_device_flash_all.1534511867804010589209208376628825680205355141963608115586244530829973596611
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:df7a5ea0-4e36-42ac-a081-3f1fe167b1c8
... and 43 more failures.
0.spi_device_flash_and_tpm.1908921014904579757845719479967674982256283599324359369607911929539675125453
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:81fde408-adc6-4bbb-9251-7945ba39e373
1.spi_device_flash_and_tpm.18024076714894894044434496576735238063778083048469095879289925097340032873431
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:6f3d5201-b28b-48e6-a05c-f1e5d144d32e
... and 44 more failures.
0.spi_device_stress_all.73598842787480038775329318269232885814385724199337828847304231728974809906369
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest/run.log
Job ID: smart:d5440314-656d-4d21-be11-7b824d2e4c6c
1.spi_device_stress_all.85743997424607263558202112895655647436661277845294889081194931127343209372567
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest/run.log
Job ID: smart:5996b67b-dac5-424a-aa88-c93824556978
... and 35 more failures.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 22 failures:
Test spi_device_flash_and_tpm_min_idle has 5 failures.
0.spi_device_flash_and_tpm_min_idle.87223367501428771337517848267092735209824716641505051627019123557644965291312
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 366829330 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 366829330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_device_flash_and_tpm_min_idle.32110784361576589806921600550271117298106336596978556127836823250453522223500
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 114585165 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 114585165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_device_upload has 10 failures.
2.spi_device_upload.34201314440442085596616084096199362271698390267480962833643453108715369468214
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest/run.log
UVM_FATAL @ 2374677804 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2374677804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_device_upload.81086788946780742628235089872530380815352620413904793379268886755840859410451
Line 262, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest/run.log
UVM_FATAL @ 12652748695 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12652748695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test spi_device_flash_all has 3 failures.
13.spi_device_flash_all.43946525639287876796815309147587713225123098602904002903411575801964556050114
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest/run.log
UVM_FATAL @ 96500964 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 96500964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_device_flash_all.67968858125385126886117442562317966267095339731289793809884288415203502606379
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest/run.log
UVM_FATAL @ 106914539 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 106914539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_device_flash_and_tpm has 2 failures.
18.spi_device_flash_and_tpm.10039196365400327936751862936560614410154335870096387496996395792234937518881
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 349134356 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 349134356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.spi_device_flash_and_tpm.78806420338623992417443323093081252008327167798818698912876908928545904503546
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 39577214 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 39577214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_stress_all has 2 failures.
20.spi_device_stress_all.83203550571294368789984374657922838680793191730130518270845854018000875971288
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest/run.log
UVM_FATAL @ 659137792 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 659137792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_device_stress_all.37268451810325726576712550477692459412472371852541711900659905195764229330202
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest/run.log
UVM_FATAL @ 539638467 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 539638467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 22 failures:
Test spi_device_cfg_cmd has 9 failures.
3.spi_device_cfg_cmd.102357595486643440857106060374758684552944229523846952686835704703454981453882
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 200564071 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 201497395 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 202797382 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xdd9b66) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3766d9, wel:'h0, busy:'h0}, '{other_status:'h3766d9, wel:'h0, busy:'h0}}
UVM_INFO @ 203330710 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x4
UVM_ERROR @ 203630707 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xdd9b66) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3766d9, wel:'h0, busy:'h0}, '{other_status:'h3766d9, wel:'h0, busy:'h0}}
4.spi_device_cfg_cmd.24785015106482515884556579343295778433075968762856763285366395512534220765653
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 409518952 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x89fc36) != exp '{'{other_status:'h227f0d, wel:'h0, busy:'h0}, '{other_status:'h227f0d, wel:'h0, busy:'h0}}
UVM_INFO @ 412413712 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0xe9
UVM_ERROR @ 413124244 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x89fc36) != exp '{'{other_status:'h227f0d, wel:'h0, busy:'h0}, '{other_status:'h227f0d, wel:'h0, busy:'h0}, '{other_status:'h307e53, wel:'h0, busy:'h0}}
UVM_ERROR @ 414150568 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x89fc36) != exp '{'{other_status:'h227f0d, wel:'h0, busy:'h0}, '{other_status:'h227f0d, wel:'h0, busy:'h0}, '{other_status:'h307e53, wel:'h0, busy:'h0}}
UVM_ERROR @ 414334780 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x89fc36) != exp '{'{other_status:'h227f0d, wel:'h0, busy:'h0}, '{other_status:'h227f0d, wel:'h0, busy:'h0}, '{other_status:'h307e53, wel:'h0, busy:'h0}}
... and 7 more failures.
Test spi_device_upload has 7 failures.
6.spi_device_upload.96376198861377555179321117749138238443199177741301784684779968615195011763506
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest/run.log
UVM_ERROR @ 4719860379 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 4728579408 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 4729382041 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 12, test op = 0xe9
UVM_INFO @ 4730528085 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 13, test op = 0xb7
UVM_INFO @ 4731564368 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 14, test op = 0xa8
15.spi_device_upload.92640885055299325939121860987284929591808988192407706311190182931467992010833
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest/run.log
UVM_ERROR @ 2261489629 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 2312346721 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 2312786847 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 10, test op = 0x70
UVM_INFO @ 2497042603 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 11, test op = 0xb
UVM_INFO @ 2531430882 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 12, test op = 0xaf
... and 5 more failures.
Test spi_device_flash_all has 1 failures.
8.spi_device_flash_all.23848313709330533838061945622268695444172244248947865918481915070494846162314
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest/run.log
UVM_ERROR @ 107931500 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 144101500 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 406941500 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 1/2
UVM_ERROR @ 538991500 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1bc1d) != exp '{'{other_status:'h6f07, wel:'h0, busy:'h0}, '{other_status:'h6f07, wel:'h0, busy:'h0}}
UVM_ERROR @ 691991500 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9b8245) != exp '{'{other_status:'h26e091, wel:'h0, busy:'h0}, '{other_status:'h26e091, wel:'h0, busy:'h0}}
Test spi_device_flash_and_tpm_min_idle has 2 failures.
23.spi_device_flash_and_tpm_min_idle.19905497683270752718881769691835317131157717499755451077021608005851425010396
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 26111573 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 27384574 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 27384574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.spi_device_flash_and_tpm_min_idle.83666534305237755193891251641771774778475819403247398999766099834661833325995
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 1214573417 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 1220448468 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1220448468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 2 failures.
31.spi_device_flash_and_tpm.3672125192740094663807280111107803477820810635553101110787288100174356435761
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 152016687 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 4758428538 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 10250097471 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 10274637135 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10274637135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
37.spi_device_flash_and_tpm.27515769151424066814264663190130122958829825092797957947358093272514391229713
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 722945841 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x773189) != exp '{'{other_status:'h1dcc62, wel:'h0, busy:'h0}, '{other_status:'h1dcc62, wel:'h0, busy:'h0}}
UVM_ERROR @ 827984242 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x773189) != exp '{'{other_status:'h1dcc62, wel:'h0, busy:'h0}, '{other_status:'h1dcc62, wel:'h0, busy:'h0}}
UVM_ERROR @ 970949454 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x773189) != exp '{'{other_status:'h1dcc62, wel:'h0, busy:'h0}, '{other_status:'h1dcc62, wel:'h0, busy:'h0}}
UVM_INFO @ 1011628768 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/20
UVM_INFO @ 1093729644 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/20
... and 1 more tests.
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
0.spi_device_mem_parity.7184424136767648574864443376322611804973478942237572845289958538399986016741
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 769840 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[52])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 769840 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 769840 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[948])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.24033403683125698051912706939804842724679588514425117372665010796100594833515
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 1092611 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[102])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1092611 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1092611 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[998])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 4 failures:
7.spi_device_cfg_cmd.54005694971444849792405265778514933428062261862068229802229666366862628216069
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 550221794 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x579596) != exp '{'{other_status:'h2bb3e5, wel:'h0, busy:'h0}, '{other_status:'h15e565, wel:'h0, busy:'h0}, '{other_status:'h15e565, wel:'h0, busy:'h0}}
UVM_ERROR @ 550253045 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x579596) != exp '{'{other_status:'h2bb3e5, wel:'h0, busy:'h0}, '{other_status:'h15e565, wel:'h0, busy:'h0}, '{other_status:'h15e565, wel:'h0, busy:'h0}}
UVM_ERROR @ 550450968 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x579596) != exp '{'{other_status:'h2bb3e5, wel:'h0, busy:'h0}, '{other_status:'h15e565, wel:'h0, busy:'h0}, '{other_status:'h15e565, wel:'h0, busy:'h0}, '{other_status:'h3a3ca6, wel:'h0, busy:'h0}}
UVM_ERROR @ 550638474 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x579596) != exp '{'{other_status:'h2bb3e5, wel:'h0, busy:'h0}, '{other_status:'h15e565, wel:'h0, busy:'h0}, '{other_status:'h15e565, wel:'h0, busy:'h0}, '{other_status:'h3a3ca6, wel:'h0, busy:'h0}}
UVM_ERROR @ 551190575 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x579596) != exp '{'{other_status:'h2bb3e5, wel:'h0, busy:'h0}, '{other_status:'h15e565, wel:'h0, busy:'h0}, '{other_status:'h15e565, wel:'h0, busy:'h0}, '{other_status:'h3a3ca6, wel:'h0, busy:'h0}}
14.spi_device_cfg_cmd.91971985508129283976232649730926632398453216164241249652304331486318710145897
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 6882216715 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5c989a) != exp '{'{other_status:'h172626, wel:'h0, busy:'h0}, '{other_status:'h172626, wel:'h0, busy:'h0}, '{other_status:'h34844f, wel:'h0, busy:'h0}}
UVM_ERROR @ 6883550043 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5c989a) != exp '{'{other_status:'h172626, wel:'h0, busy:'h0}, '{other_status:'h172626, wel:'h0, busy:'h0}, '{other_status:'h34844f, wel:'h0, busy:'h0}}
UVM_ERROR @ 6883966708 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5c989a) != exp '{'{other_status:'h172626, wel:'h0, busy:'h0}, '{other_status:'h34844f, wel:'h0, busy:'h0}, '{other_status:'h34844f, wel:'h0, busy:'h0}}
UVM_ERROR @ 6885050037 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xd2113e) != exp '{'{other_status:'h172626, wel:'h0, busy:'h0}, '{other_status:'h34844f, wel:'h0, busy:'h0}, '{other_status:'h34844f, wel:'h0, busy:'h0}}
UVM_INFO @ 6886633364 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 7, test op = 0xe9
... and 1 more failures.
42.spi_device_flash_all.3011404864200124438116160475268426516241425540045330667389793443447677782618
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest/run.log
UVM_ERROR @ 835067533 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3a9de0, wel:'h0, busy:'h0}}
UVM_ERROR @ 967943596 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xea7782) != exp '{'{other_status:'h3a9de0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3a9de0, wel:'h0, busy:'h0}, '{other_status:'h3a9de0, wel:'h0, busy:'h0}}
UVM_ERROR @ 1011831396 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3a9de0, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 1012164724 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3a9de0, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 1012498052 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3a9de0, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR (spi_device_scoreboard.sv:969) scoreboard [scoreboard] WEL mismatch: act=*, pred_fuzzy_q ('{'{other_status:*, wel:*, busy:*}} ) pred=* has 1 failures:
3.spi_device_flash_and_tpm_min_idle.83024107849745572834693013197212119972844725557937291754328278216521176790118
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 2350509521 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h102c14, wel:'h0, busy:'h0}} ) pred=0x0
UVM_FATAL @ 2350529522 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2350529522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_device_scoreboard.sv:1124) [scoreboard] timeout occurred! has 1 failures:
23.spi_device_flash_mode.35392343260612234357400341908764025334424715977062870291933085542328464873875
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest/run.log
UVM_FATAL @ 21817507417 ps: (spi_device_scoreboard.sv:1124) [uvm_test_top.env.scoreboard] timeout occurred!
UVM_INFO @ 21817507417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---