4fd94db59a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 33.510s | 5.882ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.370s | 41.760us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.630s | 253.087us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 38.420s | 9.488ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 20.750s | 758.693us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.880s | 270.380us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.630s | 253.087us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 20.750s | 758.693us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.710s | 18.347us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 2.360s | 76.296us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.830s | 33.733us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.750s | 13.476us | 0 | 20 | 0.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.750s | 17.038us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 13.710s | 556.186us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 13.710s | 556.186us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 30.230s | 83.148ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.240s | 171.351us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.152m | 12.603ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 35.240s | 29.824ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 37.530s | 59.695ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 37.530s | 59.695ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 44.160s | 20.512ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 44.160s | 20.512ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 44.160s | 20.512ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 44.160s | 20.512ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 44.160s | 20.512ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 55.170s | 83.353ms | 36 | 50 | 72.00 |
| V2 | mailbox_command | spi_device_mailbox | 2.192m | 37.243ms | 42 | 50 | 84.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 2.192m | 37.243ms | 42 | 50 | 84.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 2.192m | 37.243ms | 42 | 50 | 84.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 3.802m | 19.041ms | 46 | 50 | 92.00 |
| spi_device_read_buffer_direct | 23.240s | 4.689ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 2.192m | 37.243ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 55.300s | 27.391ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 37.720s | 5.701ms | 22 | 50 | 44.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 37.720s | 5.701ms | 22 | 50 | 44.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 33.510s | 5.882ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 1.285m | 7.646ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 47.810s | 21.550ms | 14 | 50 | 28.00 |
| V2 | alert_test | spi_device_alert_test | 0.780s | 13.287us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.780s | 16.146us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.530s | 907.740us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 5.530s | 907.740us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.370s | 41.760us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.630s | 253.087us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 20.750s | 758.693us | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.080s | 612.834us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.370s | 41.760us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.630s | 253.087us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 20.750s | 758.693us | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.080s | 612.834us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 745 | 961 | 77.52 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.180s | 302.795us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 23.500s | 1.056ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 23.500s | 1.056ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 835 | 1101 | 75.84 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 13 | 59.09 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.03 | 97.50 | 92.82 | 98.61 | 80.85 | 95.87 | 90.96 | 87.59 |
Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 204 failures:
0.spi_device_cfg_cmd.19707609160796548171733936664821728713662814797550186825753505765527786227795
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
Job ID: smart:0f8071e2-2f6e-475a-97cc-a0e6035e4f74
3.spi_device_cfg_cmd.79455840317631662176151690720074719001098305275285870699550063766941178055344
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest/run.log
Job ID: smart:7193953f-96fb-4a8c-aa8f-575b7c8f346a
... and 20 more failures.
0.spi_device_flash_and_tpm.7751434516341762693572213081946028743962701271271356292444688477453721474497
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:f847c41b-f352-4986-a25b-aef5fcdb4505
1.spi_device_flash_and_tpm.48013306404290821635561726220723690028838472607290264547276040175670776723717
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:d02c233a-4f78-421a-bb70-254b079c063c
... and 43 more failures.
0.spi_device_flash_and_tpm_min_idle.70865293104065384025091846983592254001590261845787894903692459113094565308932
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:c458e9a3-6198-4220-a7a5-4d36ecc10773
3.spi_device_flash_and_tpm_min_idle.9793539378214010518396786230731602873469754954391179808546729654166754563232
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:7c23eb22-b1c6-46a5-b72b-acf98ff5690b
... and 41 more failures.
1.spi_device_stress_all.13550940392338038684801928953418056502890830577189507387117231563198396265093
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest/run.log
Job ID: smart:cfdd720a-673a-4130-8ac4-457450076700
5.spi_device_stress_all.109822165402330136914986046138550929103282957170002497063793974736916672299518
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest/run.log
Job ID: smart:58e81cc6-05ad-4e4a-b121-6cecb7d8b048
... and 30 more failures.
2.spi_device_flash_mode.94449714527399406652335341394529350688091065008718515145819691086819245203778
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest/run.log
Job ID: smart:74982653-34f3-4f0a-9f1b-678d57aab57c
20.spi_device_flash_mode.96080054915858324349120231669872522043908829945258462691336943924197948975634
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest/run.log
Job ID: smart:347a2d55-5535-4a01-bd7c-f986481d6a56
... and 2 more failures.
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
0.spi_device_mem_parity.101171341722220622250075444367847827618863066665330235029978827006939769830129
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 10809541 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[65])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 10809541 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 10809541 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[961])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.35729563664160337188921219267106192226998324664493000078523839073474405272754
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 3278397 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[84])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3278397 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3278397 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[980])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 19 failures:
Test spi_device_flash_all has 2 failures.
1.spi_device_flash_all.54443357506973128720598567183687083297540438441792762681154860151320819761004
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
UVM_FATAL @ 619116842 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 619116842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_device_flash_all.111247654626961641991995042308344254266757260729570503098643695477581529664023
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest/run.log
UVM_FATAL @ 1958571742 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1958571742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm_min_idle has 4 failures.
1.spi_device_flash_and_tpm_min_idle.101969014977315381352210850096372230411566668051418450521251985747658612697728
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 97989930 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 97989930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_device_flash_and_tpm_min_idle.29664017785816900420701569453200871631258396609149880899317904054918769833570
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 556509542 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 556509542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_upload has 8 failures.
3.spi_device_upload.96860174392775274763995092566027314656357704835082859371429473729272167686312
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest/run.log
UVM_FATAL @ 1573139829 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1573139829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_device_upload.84232209754870031436195791484807613302933882138738612080603067376616110218225
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest/run.log
UVM_FATAL @ 81193299 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 81193299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test spi_device_stress_all has 2 failures.
3.spi_device_stress_all.113974707359188754081055645231890554282526464461569319037094311105832390431997
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest/run.log
UVM_FATAL @ 13344602629 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13344602629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.spi_device_stress_all.65179049081576002587608494489820981244056218540491221500616143021742473503451
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest/run.log
UVM_FATAL @ 5081702820 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5081702820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 3 failures.
9.spi_device_flash_and_tpm.109851791316602712065420979707207910176039453691830547230773280734474958001628
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 1693062569 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1693062569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_device_flash_and_tpm.73848821483248864063043328814985823943144232871763898271327809434833253379485
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 195753848 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 195753848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 17 failures:
Test spi_device_flash_and_tpm_min_idle has 2 failures.
2.spi_device_flash_and_tpm_min_idle.68735233920371445251024572246097223472273798405977334790207195944132040999676
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 652581079 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 653730747 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 653730747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.spi_device_flash_and_tpm_min_idle.113448190108419911088518191708267432643574856415093913315844190895800342452527
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 7643834085 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe7fabd) != exp '{'{other_status:'h39feaf, wel:'h0, busy:'h0}, '{other_status:'h39feaf, wel:'h0, busy:'h0}}
UVM_FATAL @ 7645628445 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7645628445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_cfg_cmd has 4 failures.
4.spi_device_cfg_cmd.20777984941883688487117449053123997091076611695381133842908517262874944119971
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 299611835 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8840c6) != exp '{'{other_status:'h221031, wel:'h0, busy:'h0}, '{other_status:'h221031, wel:'h0, busy:'h0}}
UVM_ERROR @ 300468971 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8840c6) != exp '{'{other_status:'h221031, wel:'h0, busy:'h0}, '{other_status:'h221031, wel:'h0, busy:'h0}}
UVM_ERROR @ 301958755 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8840c6) != exp '{'{other_status:'h221031, wel:'h0, busy:'h0}, '{other_status:'h221031, wel:'h0, busy:'h0}, '{other_status:'h2fdf06, wel:'h0, busy:'h0}}
UVM_ERROR @ 302387323 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8840c6) != exp '{'{other_status:'h221031, wel:'h0, busy:'h0}, '{other_status:'h221031, wel:'h0, busy:'h0}, '{other_status:'h2fdf06, wel:'h0, busy:'h0}}
UVM_ERROR @ 302489363 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8840c6) != exp '{'{other_status:'h221031, wel:'h0, busy:'h0}, '{other_status:'h221031, wel:'h0, busy:'h0}, '{other_status:'h2fdf06, wel:'h0, busy:'h0}}
25.spi_device_cfg_cmd.78294473729671518354147526412158673926077754864763421212880793273897613317383
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 525660726 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xefbbaa) != exp '{'{other_status:'h3beeea, wel:'h0, busy:'h0}, '{other_status:'h3beeea, wel:'h0, busy:'h0}}
UVM_ERROR @ 526040039 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xefbbaa) != exp '{'{other_status:'h3beeea, wel:'h0, busy:'h0}, '{other_status:'h3beeea, wel:'h0, busy:'h0}}
UVM_ERROR @ 527005563 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xefbbaa) != exp '{'{other_status:'h3beeea, wel:'h0, busy:'h0}, '{other_status:'h3beeea, wel:'h0, busy:'h0}}
UVM_INFO @ 527453842 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0xe9
UVM_ERROR @ 528695230 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xefbbaa) != exp '{'{other_status:'h3beeea, wel:'h0, busy:'h0}, '{other_status:'h3beeea, wel:'h0, busy:'h0}}
... and 2 more failures.
Test spi_device_upload has 6 failures.
7.spi_device_upload.43557761351438115498759220643917689874622834820761712369125887289172678904827
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest/run.log
UVM_ERROR @ 5832648270 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 6118848270 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 6122465270 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0xb
UVM_INFO @ 7314408270 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x35
UVM_INFO @ 12958215270 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0x6a
8.spi_device_upload.67007467327373010704591051025822632226452481977838111194236295063090172356225
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest/run.log
UVM_ERROR @ 1033397405 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 1035847405 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 1036769405 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0x1b
UVM_INFO @ 1039969405 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 7, test op = 0x16
UVM_INFO @ 1972619405 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 8, test op = 0x6b
... and 4 more failures.
Test spi_device_flash_all has 2 failures.
7.spi_device_flash_all.11642431814317847000784770428720275210519243443441961122125580382759108608194
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest/run.log
UVM_ERROR @ 847782551 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x48faca) != exp '{'{other_status:'h123eb2, wel:'h0, busy:'h0}, '{other_status:'h123eb2, wel:'h0, busy:'h0}}
UVM_FATAL @ 973961118 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 973961118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_device_flash_all.101837158446561000676258064736999315039522983644011733687083846303471776227748
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest/run.log
UVM_ERROR @ 27388544767 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x87e15f) != exp '{'{other_status:'h21f857, wel:'h0, busy:'h0}, '{other_status:'h21f857, wel:'h0, busy:'h0}}
UVM_FATAL @ 27391314032 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 27391314032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 1 failures.
15.spi_device_flash_and_tpm.19389773772207237944983244763317232480476213140076624120824157595771298087577
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 1078564627 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 1124118068 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1124118068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 5 failures:
Test spi_device_flash_all has 2 failures.
0.spi_device_flash_all.82883857627620043123654580060630181635607013080152322658322386980521784642849
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
UVM_ERROR @ 2933913772 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2aa8ea) != exp '{'{other_status:'h355d8f, wel:'h0, busy:'h0}, '{other_status:'haaa3a, wel:'h0, busy:'h0}, '{other_status:'haaa3a, wel:'h0, busy:'h0}}
UVM_ERROR @ 2935056603 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 2935437547 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 2935818491 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 2936199435 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
22.spi_device_flash_all.115245314114910558476010925362620432497764287824448897612335990104542246623232
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest/run.log
UVM_ERROR @ 2195655553 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h245d19, wel:'h0, busy:'h0}}
UVM_ERROR @ 3495121831 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h245d19, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 3495627079 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h245d19, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 3496132327 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h245d19, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 3496637575 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h245d19, wel:'h0, busy:'h0}} ) pred=0x0
Test spi_device_cfg_cmd has 2 failures.
16.spi_device_cfg_cmd.104625719508679643358604092880186604301627863164283706068793254627838422801072
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 44196630 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3b7a05, wel:'h0, busy:'h0}}
UVM_INFO @ 46176206 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x4
UVM_ERROR @ 46502734 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xede816) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3b7a05, wel:'h0, busy:'h0}, '{other_status:'h3b7a05, wel:'h0, busy:'h0}}
UVM_ERROR @ 46788446 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xede816) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3b7a05, wel:'h0, busy:'h0}, '{other_status:'h3b7a05, wel:'h0, busy:'h0}}
UVM_ERROR @ 47278238 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xede816) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3b7a05, wel:'h0, busy:'h0}, '{other_status:'h3b7a05, wel:'h0, busy:'h0}}
34.spi_device_cfg_cmd.88322443336453817204376962089481158227828830625624950832991472901969288455877
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 29275180 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2d50b, wel:'h0, busy:'h0}}
UVM_INFO @ 29595172 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0xe9
UVM_ERROR @ 30141825 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xb542e) != exp '{'{other_status:'h2d50b, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2d50b, wel:'h0, busy:'h0}, '{other_status:'h2d50b, wel:'h0, busy:'h0}}
UVM_ERROR @ 30635146 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xb542e) != exp '{'{other_status:'h2d50b, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2d50b, wel:'h0, busy:'h0}, '{other_status:'h2d50b, wel:'h0, busy:'h0}}
UVM_ERROR @ 30808475 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xb542e) != exp '{'{other_status:'h2d50b, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2d50b, wel:'h0, busy:'h0}, '{other_status:'h2d50b, wel:'h0, busy:'h0}}
Test spi_device_flash_and_tpm_min_idle has 1 failures.
26.spi_device_flash_and_tpm_min_idle.16789761057875862795710098134824164236166470277671720879045098483201516993001
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 2645490126 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9e2be6) != exp '{'{other_status:'h278af9, wel:'h0, busy:'h0}, '{other_status:'h278af9, wel:'h0, busy:'h0}, '{other_status:'h298f03, wel:'h0, busy:'h0}}
UVM_FATAL @ 3375081789 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3375081789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
47.spi_device_flash_and_tpm.26559142672401022027940596946251777974270192194740326371906856094594639293341
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 773316306 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xac2e92) != exp '{'{other_status:'h2b0ba4, wel:'h0, busy:'h0}, '{other_status:'h3d34b2, wel:'h0, busy:'h0}, '{other_status:'h2b0ba4, wel:'h0, busy:'h0}, '{other_status:'h2b0ba4, wel:'h0, busy:'h0}}
UVM_ERROR @ 836208135 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xac2e92) != exp '{'{other_status:'h2b0ba4, wel:'h0, busy:'h0}, '{other_status:'h3d34b2, wel:'h0, busy:'h0}, '{other_status:'h2b0ba4, wel:'h0, busy:'h0}, '{other_status:'h2b0ba4, wel:'h0, busy:'h0}}
UVM_INFO @ 945937755 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/15
UVM_INFO @ 1149342957 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/15
UVM_INFO @ 1651882995 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/15