41bc3e0c7f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 26.080s | 10.251ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.390s | 148.822us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.820s | 663.080us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 25.080s | 5.037ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 14.990s | 230.016us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 4.040s | 192.169us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.820s | 663.080us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 14.990s | 230.016us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.670s | 20.327us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 2.040s | 105.293us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.860s | 83.451us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.740s | 3.180us | 0 | 20 | 0.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.720s | 30.487us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 9.200s | 563.860us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 9.200s | 563.860us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 30.810s | 40.573ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.250s | 242.974us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.179m | 52.020ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 50.910s | 86.904ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 52.190s | 73.948ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 52.190s | 73.948ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 42.580s | 4.666ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 42.580s | 4.666ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 42.580s | 4.666ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 42.580s | 4.666ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 42.580s | 4.666ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 1.041m | 118.510ms | 41 | 50 | 82.00 |
| V2 | mailbox_command | spi_device_mailbox | 1.597m | 49.650ms | 42 | 50 | 84.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 1.597m | 49.650ms | 42 | 50 | 84.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 1.597m | 49.650ms | 42 | 50 | 84.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 2.507m | 58.747ms | 46 | 50 | 92.00 |
| spi_device_read_buffer_direct | 22.990s | 8.103ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 1.597m | 49.650ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 10.520s | 1.576ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 27.070s | 5.548ms | 17 | 50 | 34.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 27.070s | 5.548ms | 17 | 50 | 34.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 26.080s | 10.251ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 19.920s | 1.680ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 12.150s | 6.973ms | 10 | 50 | 20.00 |
| V2 | alert_test | spi_device_alert_test | 0.770s | 60.490us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.800s | 20.908us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 4.730s | 792.509us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 4.730s | 792.509us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.390s | 148.822us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.820s | 663.080us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 14.990s | 230.016us | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.400s | 162.523us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.390s | 148.822us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.820s | 663.080us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 14.990s | 230.016us | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.400s | 162.523us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 739 | 961 | 76.90 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.270s | 171.820us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 23.260s | 798.935us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 23.260s | 798.935us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 829 | 1101 | 75.30 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 13 | 59.09 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.04 | 97.50 | 92.82 | 98.61 | 80.85 | 95.87 | 90.94 | 87.69 |
Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 212 failures:
0.spi_device_flash_and_tpm.37351045058467625583932294366093914164529180142263035184689563240287443065209
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:b44e118d-3d39-4a7b-9cfe-c4764d7c44a4
1.spi_device_flash_and_tpm.14545920858965773804723230143004095781325243107519429235865540138087518180306
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:9d1aea86-61f7-474a-8f77-b69c2d0aaba4
... and 44 more failures.
1.spi_device_flash_all.104699283383530828772134716710344754460649350110285164070907196748750437832193
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:c02448f1-1c02-45e8-837f-8d7f99f53727
3.spi_device_flash_all.52193267203673704218207674909247106873480230887463017405053861169385959728537
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest/run.log
Job ID: smart:c4aa2f7f-9556-4733-84f8-cba22cc26798
... and 40 more failures.
1.spi_device_flash_and_tpm_min_idle.49993952128846414689415434241136467104069932416331324304065540014365274098624
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:557e355b-9a68-40b9-9525-5edb2c0cd712
2.spi_device_flash_and_tpm_min_idle.53967245972898632955440440486204328874462109640043666952016306756787096924370
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:52bbd7c8-c0da-487d-8b1e-9d817453997a
... and 44 more failures.
2.spi_device_intercept.76029052450707550796271864325030073408449277409168934080711239937221749796114
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest/run.log
Job ID: smart:c62cceeb-daf2-4c30-b8f6-68987c47b5ec
5.spi_device_intercept.28928091970508906862287484261287548497359644057616553473362254522271601775352
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest/run.log
Job ID: smart:c6f72f65-261d-4b0b-a884-b1c0b47f9d88
... and 6 more failures.
2.spi_device_stress_all.110517733337775636939933464124249193657960028315350401553261225973740522105502
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest/run.log
Job ID: smart:30b967dd-ff19-4b05-9ac0-8d5d8a88913b
4.spi_device_stress_all.69540861886867113197654718921878661445694763955843505243658598643181540398540
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest/run.log
Job ID: smart:6a43e18c-457a-4b2c-a9f5-00918dd02b2f
... and 32 more failures.
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
0.spi_device_mem_parity.34661681231315647386541463661413131878840599518419831489579118902008183612710
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 891007 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[101])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 891007 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 891007 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[997])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.16063998724484513529580898310929358260227068583278598722882146882137981755272
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 2335036 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[61])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2335036 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2335036 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[957])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 20 failures:
Test spi_device_flash_all has 6 failures.
0.spi_device_flash_all.52208174668863850881598241815172037188261576415625098978465401985564322637013
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
UVM_FATAL @ 1575800693 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1575800693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_device_flash_all.49328712078905131487907742971319616648269228582809156657248476203704622771052
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest/run.log
UVM_FATAL @ 233059802 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 233059802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_device_flash_and_tpm_min_idle has 2 failures.
0.spi_device_flash_and_tpm_min_idle.99207799409183580783748635356585192190439366357499221376935298980931529754571
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 82971893 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 82971893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_device_flash_and_tpm_min_idle.10512353085177096651899715510342891787979724339038391592547152006520046045313
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 1679986855 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1679986855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_upload has 5 failures.
3.spi_device_upload.39682439702407785813689890377665979432913820340266442272665990288944694203152
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest/run.log
UVM_FATAL @ 197802712 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 197802712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_device_upload.99260674603713687854301432726200005349364005359657673936009081864234184285682
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest/run.log
UVM_FATAL @ 1757308559 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1757308559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_device_stress_all has 6 failures.
3.spi_device_stress_all.23645673119398937508122418049479200658612483141298178370330437830599465491971
Line 266, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest/run.log
UVM_FATAL @ 1467054271 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1467054271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_device_stress_all.105077029230196819828717118156305365601589145541366919279284550858805600886709
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest/run.log
UVM_FATAL @ 738033626 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 738033626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_device_flash_and_tpm has 1 failures.
9.spi_device_flash_and_tpm.91158175615006088961545502961572550317731396204808642493218796601411255242805
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 1418722461 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1418722461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 19 failures:
Test spi_device_flash_all has 2 failures.
5.spi_device_flash_all.104542577403831024546960013992174206805437579356892358496596488313362631883072
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest/run.log
UVM_ERROR @ 98257810 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 211056682 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 988871127 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 988871127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_device_flash_all.104768138094168439823196748791755346134166965937182688134883288524959921498313
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest/run.log
UVM_ERROR @ 281979822 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 285577663 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h2a77c, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 285907551 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h2a77c, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 286237439 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h2a77c, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 286567327 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h2a77c, wel:'h0, busy:'h0}} ) pred=0x0
Test spi_device_cfg_cmd has 9 failures.
8.spi_device_cfg_cmd.30242262793234927085248370257531350073760016649845317175990050702052523845611
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 159462780 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 159787780 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 160287780 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0xb7
UVM_ERROR @ 160712780 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 171887780 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1a6f62, wel:'h0, busy:'h0}}
10.spi_device_cfg_cmd.86555619864009903549983527951450127484205794791963825570309024199550766685588
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 330070056 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d1bf2) != exp '{'{other_status:'h2346fc, wel:'h0, busy:'h0}, '{other_status:'h2346fc, wel:'h0, busy:'h0}}
UVM_ERROR @ 331590056 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d1bf2) != exp '{'{other_status:'h2346fc, wel:'h0, busy:'h0}, '{other_status:'h2346fc, wel:'h0, busy:'h0}}
UVM_ERROR @ 333190056 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d1bf2) != exp '{'{other_status:'h2346fc, wel:'h0, busy:'h0}, '{other_status:'h2346fc, wel:'h0, busy:'h0}, '{other_status:'h29ff0e, wel:'h0, busy:'h0}}
UVM_ERROR @ 334110056 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d1bf2) != exp '{'{other_status:'h2346fc, wel:'h0, busy:'h0}, '{other_status:'h2346fc, wel:'h0, busy:'h0}, '{other_status:'h29ff0e, wel:'h0, busy:'h0}}
UVM_ERROR @ 337510056 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d1bf2) != exp '{'{other_status:'h2346fc, wel:'h0, busy:'h0}, '{other_status:'h2346fc, wel:'h0, busy:'h0}, '{other_status:'h29ff0e, wel:'h0, busy:'h0}}
... and 7 more failures.
Test spi_device_upload has 4 failures.
19.spi_device_upload.99969449904197334848897303917688644995282085242251532151117902757748176834463
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest/run.log
UVM_ERROR @ 26908530 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 83898990 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 84752696 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 1, test op = 0x5
UVM_INFO @ 131937844 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0x16
UVM_INFO @ 677917998 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x31
28.spi_device_upload.100258366535255195472863272369711063250532088060382153995062664284582372491831
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest/run.log
UVM_ERROR @ 118026147322 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 118448834914 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 118510309050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_flash_and_tpm has 3 failures.
24.spi_device_flash_and_tpm.37914586503537147070718756000976519787065123373856569123400473901097811384715
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 1031428481 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 1070173482 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1070173482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_device_flash_and_tpm.96750382145573835159904495879396985787098340793683979801427700354239486848421
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 10204580746 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 10250993137 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10250993137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_device_flash_and_tpm_min_idle has 1 failures.
44.spi_device_flash_and_tpm_min_idle.15887595979208886986431956185835144778781738498003187131657324571291188804744
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 137014855 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 266599225 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 1879987132 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 1942820968 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/7
UVM_ERROR @ 1955987740 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR (spi_device_scoreboard.sv:969) scoreboard [scoreboard] WEL mismatch: act=*, pred_fuzzy_q ('{'{other_status:*, wel:*, busy:*}} ) pred=* has 1 failures:
46.spi_device_flash_and_tpm_min_idle.90768864517427192951011768153481292721898108271599034652612660415301742238744
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 924219505 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h167cc4, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 924379505 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h167cc4, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 924539505 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h167cc4, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 924699505 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h167cc4, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 924859505 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h167cc4, wel:'h0, busy:'h0}} ) pred=0x0