SPI_DEVICE/1R1W Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	22.480s	8.186ms	0	50	0.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.340s	43.528us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.770s	382.906us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.280s	2.821ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.770s	1.225ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.910s	137.509us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.770s	382.906us	20	20	100.00
		spi_device_csr_aliasing	24.770s	1.225ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	16.948us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.080s	30.517us	5	5	100.00
V1		TOTAL			65	115	56.52
V2	csb_read	spi_device_csb_read	0.880s	56.160us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.780s	1.225us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	40.265us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	13.240s	372.420us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	13.240s	372.420us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	34.440s	51.032ms	50	50	100.00
		spi_device_tpm_sts_read	1.320s	199.101us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.181m	28.980ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	34.850s	246.197ms	50	50	100.00
		spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.360s	51.462ms	50	50	100.00
		spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.360s	51.462ms	50	50	100.00
		spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	cmd_info_slots	spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	cmd_read_status	spi_device_intercept	50.920s	16.690ms	40	50	80.00
		spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	cmd_read_jedec	spi_device_intercept	50.920s	16.690ms	40	50	80.00
		spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	cmd_read_sfdp	spi_device_intercept	50.920s	16.690ms	40	50	80.00
		spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	cmd_fast_read	spi_device_intercept	50.920s	16.690ms	40	50	80.00
		spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	cmd_read_pipeline	spi_device_intercept	50.920s	16.690ms	40	50	80.00
		spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	flash_cmd_upload	spi_device_upload	54.190s	70.587ms	32	50	64.00
V2	mailbox_command	spi_device_mailbox	2.551m	20.683ms	47	50	94.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.551m	20.683ms	47	50	94.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.551m	20.683ms	47	50	94.00
V2	cmd_read_buffer	spi_device_flash_mode	2.629m	10.517ms	44	50	88.00
		spi_device_read_buffer_direct	16.310s	1.152ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.551m	20.683ms	47	50	94.00
		spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	quad_spi	spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	dual_spi	spi_device_flash_all	19.420s	10.443ms	0	50	0.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.610s	28.902ms	21	50	42.00
V2	write_enable_disable	spi_device_cfg_cmd	25.610s	28.902ms	21	50	42.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	22.480s	8.186ms	0	50	0.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	52.220s	5.907ms	0	50	0.00
V2	stress_all	spi_device_stress_all	18.660s	1.639ms	16	50	32.00
V2	alert_test	spi_device_alert_test	0.820s	14.437us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	11.260us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.230s	1.330ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.230s	1.330ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.340s	43.528us	5	5	100.00
		spi_device_csr_rw	2.770s	382.906us	20	20	100.00
		spi_device_csr_aliasing	24.770s	1.225ms	5	5	100.00
		spi_device_same_csr_outstanding	4.320s	1.894ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.340s	43.528us	5	5	100.00
		spi_device_csr_rw	2.770s	382.906us	20	20	100.00
		spi_device_csr_aliasing	24.770s	1.225ms	5	5	100.00
		spi_device_same_csr_outstanding	4.320s	1.894ms	20	20	100.00
V2		TOTAL			741	961	77.11
V2S	tl_intg_err	spi_device_sec_cm	1.200s	85.147us	5	5	100.00
		spi_device_tl_intg_err	24.230s	2.251ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.230s	2.251ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			831	1101	75.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	13	59.09
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.09	97.50	92.83	98.61	80.85	95.89	90.94	88.03

Failure Buckets

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 213 failures:
- Test spi_device_flash_and_tpm has 48 failures.
  - 0.spi_device_flash_and_tpm.96400209446641433807258453767129421446474044671508448267955548185091832307766
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:b264d3ed-dc93-49f5-ac4d-ce631169e6b1
```
  - 1.spi_device_flash_and_tpm.43690796307248877171539736704607155705549276216762517292964037552206955219915
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:a80a96b2-c302-47b4-aa8f-1425b539570c
```
  - ... and 46 more failures.
- Test spi_device_flash_and_tpm_min_idle has 45 failures.
  - 0.spi_device_flash_and_tpm_min_idle.109948779798774522183762685085272023967155914248181187989589461920075990029888
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:6eb39fcb-8d25-4917-805d-6eb78866148a
```
  - 1.spi_device_flash_and_tpm_min_idle.78094732148770273613430119647861583555118136854909078183204638994952396488382
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:3c1d0abf-db73-4d4c-9271-2ae43d01de56
```
  - ... and 43 more failures.
- Test spi_device_intercept has 10 failures.
  - 1.spi_device_intercept.100428600131394285946740997932493567599115509761252881070213894727203876602885
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest/run.log
```
  Job ID: smart:395ec92c-5d5a-4fcd-97fe-b2b58b5778db
```
  - 2.spi_device_intercept.71141653186072861464410380480641850793475765409373189653481471054039612216698
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest/run.log
```
  Job ID: smart:28bb4060-b91d-4186-a0d2-9eacb6e27b14
```
  - ... and 8 more failures.
- Test spi_device_flash_mode has 6 failures.
  - 1.spi_device_flash_mode.101091668060826291265480456142104667887267096023876925755828487535699139748632
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest/run.log
```
  Job ID: smart:8af62ec7-e05b-4bc4-9c61-9f74cb9ce9f5
```
  - 3.spi_device_flash_mode.79962247890353605152111385443098754063495281869874374372936904923605550691171
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest/run.log
```
  Job ID: smart:8bad8fb3-18b6-41b7-b49c-6dc58580ab7f
```
  - ... and 4 more failures.
- Test spi_device_flash_all has 46 failures.
  - 1.spi_device_flash_all.113298294316948645908335381828327128515393224166755892398964270163142881922596
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
```
  Job ID: smart:8f2d8734-b0c5-4b80-af1e-4dd618b8c1e6
```
  - 2.spi_device_flash_all.86573265361548970221463697297721920427483092985997103418361685993795180540023
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest/run.log
```
  Job ID: smart:02e3529d-d919-4729-8f2d-4aa3ddda0251
```
  - ... and 44 more failures.
- ... and 3 more tests.

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.99592018682973278404597434338233285232990978005166916402137445385997479462092
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   6668757 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[93])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   6668757 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   6668757 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[989])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.51449834496955102418983799316936799326860994879486504060671149355499990339768
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2226521 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[15])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2226521 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2226521 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[911])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 19 failures:

Test spi_device_flash_all has 1 failures.

0.spi_device_flash_all.34598145102722978269060931679925188318074210397268508305576224735103595589509
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 2103605484 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 10442630512 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h11c37d, wel:'h0, busy:'h0}} ) pred=0x0
  UVM_FATAL @ 10442734681 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 10442734681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_cfg_cmd has 4 failures.

2.spi_device_cfg_cmd.30709123270349243792984248218468116056260512807325681356350202652200999954572
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 201208294 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9f675a) != exp '{'{other_status:'h27d9d6, wel:'h0, busy:'h0}, '{other_status:'h27d9d6, wel:'h0, busy:'h0}}
  UVM_ERROR @ 202106246 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9f675a) != exp '{'{other_status:'h27d9d6, wel:'h0, busy:'h0}, '{other_status:'h27d9d6, wel:'h0, busy:'h0}}
  UVM_ERROR @ 202514406 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9f675a) != exp '{'{other_status:'h27d9d6, wel:'h0, busy:'h0}, '{other_status:'h27d9d6, wel:'h0, busy:'h0}}
  UVM_ERROR @ 202902158 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9f675a) != exp '{'{other_status:'h27d9d6, wel:'h0, busy:'h0}, '{other_status:'h27d9d6, wel:'h0, busy:'h0}}
  UVM_INFO @ 203187870 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 4, test op = 0x6

5.spi_device_cfg_cmd.90549559354271266254880122837619285539660979725028322403254264333195438518888
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 209079285 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x43fa9e) != exp '{'{other_status:'h10fea7, wel:'h0, busy:'h0}, '{other_status:'h10fea7, wel:'h0, busy:'h0}}
  UVM_ERROR @ 209679285 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x43fa9e) != exp '{'{other_status:'h10fea7, wel:'h0, busy:'h0}, '{other_status:'h10fea7, wel:'h0, busy:'h0}}
  UVM_ERROR @ 209899285 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x43fa9e) != exp '{'{other_status:'h10fea7, wel:'h0, busy:'h0}, '{other_status:'h10fea7, wel:'h0, busy:'h0}}
  UVM_INFO @ 210339285 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0x4
  UVM_ERROR @ 210539285 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x43fa9e) != exp '{'{other_status:'h10fea7, wel:'h0, busy:'h0}, '{other_status:'h10fea7, wel:'h0, busy:'h0}}

... and 2 more failures.

Test spi_device_upload has 10 failures.

3.spi_device_upload.7292975327836910380581056097969419099347143067073577772357152201505308549966
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest/run.log

  UVM_ERROR @ 10169702835 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 12204622835 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 12207469835 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 8, test op = 0xb7
  UVM_INFO @ 16801132835 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 9, test op = 0xf5
  UVM_INFO @ 16803738835 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 10, test op = 0x5

9.spi_device_upload.38668436485812084703587501410280118170709408604376304632459853241032928782201
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest/run.log

  UVM_ERROR @ 4336716450 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 5019037522 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 5020051188 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 10, test op = 0x78
  UVM_INFO @ 5054052712 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 11, test op = 0xb
  UVM_INFO @ 5448546576 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 12, test op = 0x39

... and 8 more failures.

Test spi_device_stress_all has 1 failures.

17.spi_device_stress_all.28395710912932318486952340531245358230325536234784945947198465960452718832732
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest/run.log

  UVM_ERROR @  99897635 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 102558580 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 102558580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm_min_idle has 2 failures.

29.spi_device_flash_and_tpm_min_idle.63733052887319726970127984305473467870121668575799629553636726461105263756187
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 444895180 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1947607183 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 5428348252 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 5904005512 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xfdf13d) != exp '{'{other_status:'h3f7c4f, wel:'h0, busy:'h0}, '{other_status:'h3f7c4f, wel:'h0, busy:'h0}}
  UVM_FATAL @ 5907299533 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])

38.spi_device_flash_and_tpm_min_idle.101056306554890469724469603974062619567956009004357774484325018195923689982369
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 125089025 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x13c8a1) != exp '{'{other_status:'h4f228, wel:'h0, busy:'h0}, '{other_status:'h4f228, wel:'h0, busy:'h0}}
  UVM_FATAL @ 137531515 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 137531515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 15 failures:
- Test spi_device_upload has 8 failures.
  - 1.spi_device_upload.67202039411904334169729853312577360613944410781345420031371369483548342022588
    Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest/run.log
```
  UVM_FATAL @  99466049 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  99466049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.spi_device_upload.65291799601686687395286017141786586251319298368981351076903314881918726413186
    Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest/run.log
```
  UVM_FATAL @  48520872 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  48520872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
- Test spi_device_flash_and_tpm_min_idle has 3 failures.
  - 23.spi_device_flash_and_tpm_min_idle.39718744080624857736791834992756788365301014966467339429174275310799290334504
    Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @ 169831702 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 169831702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.spi_device_flash_and_tpm_min_idle.35423983531951161661335088803334612311966060903760333396759360644738817951050
    Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @ 5376974271 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5376974271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_device_flash_all has 3 failures.
  - 26.spi_device_flash_all.87475998880413284310066978767061899482985042628107627603527842677748542630696
    Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest/run.log
```
  UVM_FATAL @ 267909980 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 267909980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.spi_device_flash_all.7108937783016327565203027597234975339495111036863452816359858787721914680540
    Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest/run.log
```
  UVM_FATAL @ 1199854070 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1199854070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_device_stress_all has 1 failures.
  - 29.spi_device_stress_all.52335953641815450921107436034042994818033283329818925151887249823464155380079
    Line 266, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 1638565648 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1638565648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test spi_device_cfg_cmd has 1 failures.

36.spi_device_cfg_cmd.98572864491816841676735289660663827407130944434907847548174161286958886680632
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 941597834 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe6674e) != exp '{'{other_status:'h3999d3, wel:'h0, busy:'h0}, '{other_status:'h1bb9e9, wel:'h0, busy:'h0}, '{other_status:'h3999d3, wel:'h0, busy:'h0}, '{other_status:'h3999d3, wel:'h0, busy:'h0}}
  UVM_ERROR @ 944797834 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe6674e) != exp '{'{other_status:'h3999d3, wel:'h0, busy:'h0}, '{other_status:'h1bb9e9, wel:'h0, busy:'h0}, '{other_status:'h3999d3, wel:'h0, busy:'h0}, '{other_status:'h3999d3, wel:'h0, busy:'h0}}
  UVM_ERROR @ 976557834 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe6674e) != exp '{'{other_status:'h3999d3, wel:'h0, busy:'h0}, '{other_status:'h1bb9e9, wel:'h0, busy:'h0}, '{other_status:'h3999d3, wel:'h0, busy:'h0}, '{other_status:'h3999d3, wel:'h0, busy:'h0}}
  UVM_INFO @ 981557834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm has 1 failures.

36.spi_device_flash_and_tpm.55176562086275195782559228127334611733032767167146473560364758826426870254656
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 1073620179 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xda89f6) != exp '{'{other_status:'h36a27d, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h36a27d, wel:'h0, busy:'h0}, '{other_status:'h36a27d, wel:'h0, busy:'h0}}
  UVM_FATAL @ 1379769872 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1379769872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_cfg_cmd has 1 failures.

11.spi_device_cfg_cmd.64800835059422668993561971835418793799245529199685938580469717298975410121403
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @  51489122 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3a2f0a) != exp '{'{other_status:'h11adf4, wel:'h0, busy:'h0}, '{other_status:'he8bc2, wel:'h0, busy:'h0}, '{other_status:'he8bc2, wel:'h0, busy:'h0}}
  UVM_ERROR @  51527584 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3a2f0a) != exp '{'{other_status:'h11adf4, wel:'h0, busy:'h0}, '{other_status:'he8bc2, wel:'h0, busy:'h0}, '{other_status:'he8bc2, wel:'h0, busy:'h0}}
  UVM_ERROR @  51758356 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3a2f0a) != exp '{'{other_status:'h11adf4, wel:'h0, busy:'h0}, '{other_status:'he8bc2, wel:'h0, busy:'h0}, '{other_status:'he8bc2, wel:'h0, busy:'h0}}
  UVM_ERROR @  52066052 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3a2f0a) != exp '{'{other_status:'h11adf4, wel:'h0, busy:'h0}, '{other_status:'he8bc2, wel:'h0, busy:'h0}, '{other_status:'he8bc2, wel:'h0, busy:'h0}}
  UVM_INFO @  53758380 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0xb7