SPI_DEVICE/1R1W Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm			0	50	0.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.400s	125.762us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.800s	119.502us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.440s	538.097us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.520s	9.054ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.690s	512.898us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.800s	119.502us	20	20	100.00
		spi_device_csr_aliasing	23.520s	9.054ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	14.504us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.970s	187.341us	5	5	100.00
V1		TOTAL			65	115	56.52
V2	csb_read	spi_device_csb_read	0.820s	23.889us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	4.616us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	43.988us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	12.100s	1.263ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.100s	1.263ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	42.550s	16.874ms	50	50	100.00
		spi_device_tpm_sts_read	1.140s	560.269us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.126m	14.160ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.040s	46.436ms	50	50	100.00
		spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	38.950s	14.414ms	50	50	100.00
		spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	38.950s	14.414ms	50	50	100.00
		spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	cmd_info_slots	spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	cmd_read_status	spi_device_intercept	43.160s	9.446ms	45	50	90.00
		spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	cmd_read_jedec	spi_device_intercept	43.160s	9.446ms	45	50	90.00
		spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	cmd_read_sfdp	spi_device_intercept	43.160s	9.446ms	45	50	90.00
		spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	cmd_fast_read	spi_device_intercept	43.160s	9.446ms	45	50	90.00
		spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	cmd_read_pipeline	spi_device_intercept	43.160s	9.446ms	45	50	90.00
		spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	flash_cmd_upload	spi_device_upload	34.690s	40.030ms	38	50	76.00
V2	mailbox_command	spi_device_mailbox	3.344m	89.436ms	41	50	82.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.344m	89.436ms	41	50	82.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.344m	89.436ms	41	50	82.00
V2	cmd_read_buffer	spi_device_flash_mode	2.949m	32.108ms	41	50	82.00
		spi_device_read_buffer_direct	20.510s	3.868ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.344m	89.436ms	41	50	82.00
		spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	quad_spi	spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	dual_spi	spi_device_flash_all	1.218m	20.228ms	0	50	0.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.410s	12.979ms	17	50	34.00
V2	write_enable_disable	spi_device_cfg_cmd	27.410s	12.979ms	17	50	34.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm			0	50	0.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	19.120s	5.314ms	0	50	0.00
V2	stress_all	spi_device_stress_all	29.420s	12.167ms	11	50	22.00
V2	alert_test	spi_device_alert_test	0.780s	14.285us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	26.699us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.660s	1.029ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.660s	1.029ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.400s	125.762us	5	5	100.00
		spi_device_csr_rw	2.800s	119.502us	20	20	100.00
		spi_device_csr_aliasing	23.520s	9.054ms	5	5	100.00
		spi_device_same_csr_outstanding	3.920s	186.368us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.400s	125.762us	5	5	100.00
		spi_device_csr_rw	2.800s	119.502us	20	20	100.00
		spi_device_csr_aliasing	23.520s	9.054ms	5	5	100.00
		spi_device_same_csr_outstanding	3.920s	186.368us	20	20	100.00
V2		TOTAL			734	961	76.38
V2S	tl_intg_err	spi_device_sec_cm	1.110s	183.069us	5	5	100.00
		spi_device_tl_intg_err	23.900s	1.060ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.900s	1.060ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			824	1101	74.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	13	59.09
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.06	97.50	92.82	98.61	80.85	95.87	90.94	87.83

Failure Buckets

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 220 failures:
- Test spi_device_cfg_cmd has 24 failures.
  - 0.spi_device_cfg_cmd.252122629287834322453297500000755919343692008003014394207752700930069447430
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
```
  Job ID: smart:88d4dd0a-21a5-48a0-8df1-13857828dbb7
```
  - 1.spi_device_cfg_cmd.45155264638941684717283853429236144657048550540512587267481373980240875812310
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
```
  Job ID: smart:f47a4d88-9fef-41b7-b1f6-fd8e57682edc
```
  - ... and 22 more failures.
- Test spi_device_flash_all has 40 failures.
  - 0.spi_device_flash_all.49341025858707148945900458545974568345168696512031696957120394776427120263474
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
```
  Job ID: smart:58aad71f-ce1e-4eff-a9b9-f06d36a67186
```
  - 1.spi_device_flash_all.50639310169811446938292589545306320416389040249839508492748762931929107853174
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
```
  Job ID: smart:54ca550f-6bb9-4e1b-9f04-64b8068f4568
```
  - ... and 38 more failures.
- Test spi_device_flash_and_tpm has 50 failures.
  - 0.spi_device_flash_and_tpm.65598231039405657504548310256039167228414380259563317380390618204942182236402
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:f35c8fce-f9ad-45de-899b-498d8f5e1881
```
  - 1.spi_device_flash_and_tpm.106536007819127474141085359146319122152698911432324370661441636528751591354340
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:0694566c-b0b4-40ce-b7bc-c21cd461ec4e
```
  - ... and 48 more failures.
- Test spi_device_flash_and_tpm_min_idle has 47 failures.
  - 0.spi_device_flash_and_tpm_min_idle.25470697813324337852599761483720356689531654463468713945520144879938214814775
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:aaf2a8f2-3178-4b7d-90de-949c3f6aea57
```
  - 1.spi_device_flash_and_tpm_min_idle.11022607544130988765747334784524030912451361179676355133183965926886399893300
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:9de2fc73-ff01-4622-87fe-c40c5603a59c
```
  - ... and 45 more failures.
- Test spi_device_stress_all has 37 failures.
  - 0.spi_device_stress_all.9364669929287262626600155923717313656624137664828357985502541180144845448138
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest/run.log
```
  Job ID: smart:2af25f36-40ed-4114-b865-8f4d96306f1b
```
  - 3.spi_device_stress_all.64785791937214368427363627705639080830352420394737927873100594639078623169718
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest/run.log
```
  Job ID: smart:7243f2d9-7c61-4af8-89dd-f84902a314d0
```
  - ... and 35 more failures.
- ... and 3 more tests.

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.96628264757396715723614618764574386592270505343607246886929703036955275045177
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    962084 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[20])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    962084 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    962084 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[916])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.24284600055786760001286964642966076353687429041495995227381239885701072614465
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    773772 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[70])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    773772 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    773772 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[966])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 18 failures:

Test spi_device_upload has 8 failures.

11.spi_device_upload.5967672913844770264773460805446080165565116544437208075649675229590679892372
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest/run.log

  UVM_ERROR @ 305761440 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 409569417 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 450246149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.spi_device_upload.17445445189029332979993531193585547068255034595224398822905138620684526074280
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest/run.log

  UVM_ERROR @ 579463530 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 587653998 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 590700550 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0x35
  UVM_INFO @ 593042881 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0x15
  UVM_INFO @ 2254963081 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0x85

... and 6 more failures.

Test spi_device_cfg_cmd has 7 failures.

16.spi_device_cfg_cmd.62156860665920799889159477615624859265354890863142046128146461008714818408576
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @  80553431 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @  81845108 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @  82345112 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0x6
  UVM_ERROR @  82511780 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 111970349 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'hc4ad4, wel:'h0, busy:'h0}}

22.spi_device_cfg_cmd.33658682274886409952427111575174687459610988250989908189850595538759733613790
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 464118830 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf6f122) != exp '{'{other_status:'h3dbc48, wel:'h0, busy:'h0}, '{other_status:'h3dbc48, wel:'h0, busy:'h0}}
  UVM_ERROR @ 464547395 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf6f122) != exp '{'{other_status:'h3dbc48, wel:'h0, busy:'h0}, '{other_status:'h3dbc48, wel:'h0, busy:'h0}}
  UVM_ERROR @ 465575951 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf6f122) != exp '{'{other_status:'h3dbc48, wel:'h0, busy:'h0}, '{other_status:'h3dbc48, wel:'h0, busy:'h0}}
  UVM_ERROR @ 466061658 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf6f122) != exp '{'{other_status:'h3dbc48, wel:'h0, busy:'h0}, '{other_status:'h3dbc48, wel:'h0, busy:'h0}}
  UVM_INFO @ 466633078 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 9, test op = 0xb7

... and 5 more failures.

Test spi_device_flash_all has 3 failures.

22.spi_device_flash_all.13851720405119010928433527867954576937699633296725195712300349452335652583591
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 3707939672 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 4954004388 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 5045329791 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 7972381906 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 7977398299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

26.spi_device_flash_all.114413669095981959967133232592672197537521028127037017403566473605572832628400
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 7702391991 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 8301970991 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 1/7
  UVM_ERROR @ 8354751991 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h13e429, wel:'h0, busy:'h0}}
  UVM_INFO @ 17243402991 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/7
  UVM_FATAL @ 20227591992 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])

... and 1 more failures.

UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 16 failures:

Test spi_device_flash_and_tpm_min_idle has 3 failures.
- 3.spi_device_flash_and_tpm_min_idle.98926080149218191849179554147792778198253531911044708032078538282187352382578
  Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @ 225205474 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 225205474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- 22.spi_device_flash_and_tpm_min_idle.2571176846956878036291288227215493217757679668706363440159117771949593605177
  Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @ 299682368 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 299682368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- ... and 1 more failures.

Test spi_device_flash_all has 7 failures.

5.spi_device_flash_all.36492385495903340444410757628774176825093270272906974311077687507868834853700
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest/run.log

  UVM_FATAL @ 2655808306 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2655808306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.spi_device_flash_all.32425491438178971044348740310419960266500412758717186088107867156808972076772
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest/run.log

  UVM_FATAL @ 4075923494 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4075923494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test spi_device_upload has 4 failures.

16.spi_device_upload.72174260284341467668414999836360845915362455880356884105589711380635724015080
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest/run.log

  UVM_FATAL @ 844647799 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 844647799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.spi_device_upload.98581258920406306459654315220268428341840170182105931975882825464653859522777
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest/run.log

  UVM_FATAL @ 565581068 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 565581068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test spi_device_stress_all has 2 failures.

35.spi_device_stress_all.13060578312095359315438233731791694140629936970697520791274728278622835909213
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest/run.log

  UVM_FATAL @ 284880984 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 284880984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.spi_device_stress_all.14851809876337712891774495134910141498565080663064250086479009399862552316084
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest/run.log

  UVM_FATAL @ 12167491882 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 12167491882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_cfg_cmd has 2 failures.

11.spi_device_cfg_cmd.38684627764656342771603182408176943524453227274819791681702833049280101349251
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 168968135 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe380de) != exp '{'{other_status:'h301278, wel:'h0, busy:'h0}, '{other_status:'h38e037, wel:'h0, busy:'h0}, '{other_status:'h38e037, wel:'h0, busy:'h0}}
  UVM_INFO @ 169160054 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0xe9
  UVM_ERROR @ 170099447 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe380de) != exp '{'{other_status:'h301278, wel:'h0, busy:'h0}, '{other_status:'h38e037, wel:'h0, busy:'h0}, '{other_status:'h38e037, wel:'h0, busy:'h0}}
  UVM_ERROR @ 170271164 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe380de) != exp '{'{other_status:'h301278, wel:'h0, busy:'h0}, '{other_status:'h38e037, wel:'h0, busy:'h0}, '{other_status:'h38e037, wel:'h0, busy:'h0}}
  UVM_ERROR @ 170351972 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe380de) != exp '{'{other_status:'h301278, wel:'h0, busy:'h0}, '{other_status:'h38e037, wel:'h0, busy:'h0}, '{other_status:'h38e037, wel:'h0, busy:'h0}}

14.spi_device_cfg_cmd.104450801333762967282166216422986183797021442982990202437639653314184704850296
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 448305289 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe8dfd2) != exp '{'{other_status:'h3a37f4, wel:'h0, busy:'h0}, '{other_status:'h23f904, wel:'h0, busy:'h0}, '{other_status:'h23f904, wel:'h0, busy:'h0}}
  UVM_ERROR @ 448378208 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe8dfd2) != exp '{'{other_status:'h3a37f4, wel:'h0, busy:'h0}, '{other_status:'h23f904, wel:'h0, busy:'h0}, '{other_status:'h23f904, wel:'h0, busy:'h0}}
  UVM_ERROR @ 448753220 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe8dfd2) != exp '{'{other_status:'h3a37f4, wel:'h0, busy:'h0}, '{other_status:'h23f904, wel:'h0, busy:'h0}, '{other_status:'h23f904, wel:'h0, busy:'h0}}
  UVM_ERROR @ 448982394 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe8dfd2) != exp '{'{other_status:'h3a37f4, wel:'h0, busy:'h0}, '{other_status:'h23f904, wel:'h0, busy:'h0}, '{other_status:'h23f904, wel:'h0, busy:'h0}}
  UVM_ERROR @ 449138649 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe8dfd2) != exp '{'{other_status:'h3a37f4, wel:'h0, busy:'h0}, '{other_status:'h23f904, wel:'h0, busy:'h0}, '{other_status:'h23f904, wel:'h0, busy:'h0}}

UVM_FATAL (spi_device_scoreboard.sv:1124) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 15.spi_device_flash_mode.78848537996721045726251123220344264831838528202421114958355965804771681278344
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 58933832501 ps: (spi_device_scoreboard.sv:1124) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 58933832501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```