SPI_DEVICE/1R1W Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.939m	155.410ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	42.007us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.820s	94.839us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.320s	2.603ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.660s	1.868ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.290s	660.167us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.820s	94.839us	20	20	100.00
		spi_device_csr_aliasing	22.660s	1.868ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	67.229us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.380s	212.678us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.890s	18.499us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.780s	1.427us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.770s	15.736us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.340s	553.386us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.340s	553.386us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.110s	30.937ms	50	50	100.00
		spi_device_tpm_sts_read	1.040s	320.612us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.002m	11.760ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	34.710s	13.378ms	50	50	100.00
		spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	26.540s	16.733ms	50	50	100.00
		spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	26.540s	16.733ms	50	50	100.00
		spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.650s	10.694ms	50	50	100.00
		spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.650s	10.694ms	50	50	100.00
		spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.650s	10.694ms	50	50	100.00
		spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.650s	10.694ms	50	50	100.00
		spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.650s	10.694ms	50	50	100.00
		spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	44.800s	79.330ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.181m	14.681ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.181m	14.681ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.181m	14.681ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.332m	26.249ms	50	50	100.00
		spi_device_read_buffer_direct	23.910s	2.086ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.181m	14.681ms	50	50	100.00
		spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.325m	445.945ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.430s	9.616ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.430s	9.616ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.939m	155.410ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.516m	74.954ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.489m	577.466ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	17.530us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.770s	32.141us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.230s	715.382us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.230s	715.382us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	42.007us	5	5	100.00
		spi_device_csr_rw	2.820s	94.839us	20	20	100.00
		spi_device_csr_aliasing	22.660s	1.868ms	5	5	100.00
		spi_device_same_csr_outstanding	4.040s	209.860us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	42.007us	5	5	100.00
		spi_device_csr_rw	2.820s	94.839us	20	20	100.00
		spi_device_csr_aliasing	22.660s	1.868ms	5	5	100.00
		spi_device_same_csr_outstanding	4.040s	209.860us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.210s	222.706us	5	5	100.00
		spi_device_tl_intg_err	24.140s	7.670ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.140s	7.670ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.90	98.30	94.11	98.61	89.36	97.06	95.83	98.07

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.13021452867614668171292112477999545145103387393767401408010112621397426423549
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    831490 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[17])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    831490 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    831490 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[913])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.57153926805421478623240732140475255788555491147228160191235441382680798876816
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1121096 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[108])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1121096 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1121096 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1004])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.