SPI_DEVICE/1R1W Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.594m	444.275ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	294.708us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.950s	254.935us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.960s	1.925ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.520s	1.282ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.070s	222.712us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.950s	254.935us	20	20	100.00
		spi_device_csr_aliasing	20.520s	1.282ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	12.904us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.140s	29.125us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	62.397us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.790s	1.139us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	17.172us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.970s	350.268us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.970s	350.268us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	19.670s	22.567ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	418.569us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	52.760s	10.243ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	33.200s	112.546ms	50	50	100.00
		spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	29.890s	9.061ms	50	50	100.00
		spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	29.890s	9.061ms	50	50	100.00
		spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	34.540s	13.230ms	50	50	100.00
		spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	34.540s	13.230ms	50	50	100.00
		spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.540s	13.230ms	50	50	100.00
		spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	34.540s	13.230ms	50	50	100.00
		spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.540s	13.230ms	50	50	100.00
		spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	31.500s	71.736ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.860m	18.976ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.860m	18.976ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.860m	18.976ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.422m	26.951ms	50	50	100.00
		spi_device_read_buffer_direct	24.220s	8.344ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.860m	18.976ms	50	50	100.00
		spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.628m	72.278ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	26.170s	3.147ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	26.170s	3.147ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.594m	444.275ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.468m	444.405ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.017m	78.496ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	26.879us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.850s	47.225us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.120s	65.809us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.120s	65.809us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	294.708us	5	5	100.00
		spi_device_csr_rw	2.950s	254.935us	20	20	100.00
		spi_device_csr_aliasing	20.520s	1.282ms	5	5	100.00
		spi_device_same_csr_outstanding	4.620s	1.361ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	294.708us	5	5	100.00
		spi_device_csr_rw	2.950s	254.935us	20	20	100.00
		spi_device_csr_aliasing	20.520s	1.282ms	5	5	100.00
		spi_device_same_csr_outstanding	4.620s	1.361ms	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.210s	84.657us	5	5	100.00
		spi_device_tl_intg_err	22.390s	3.686ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.390s	3.686ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.90	98.30	94.11	98.61	89.36	97.06	95.83	98.07

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.94268113515845364762524311673096778990931917680462476326489135665744547212101
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1251293 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[74])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1251293 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1251293 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[970])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.79287635720022037739884620615347653302603069826572476826899322341266812255107
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    713012 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[4])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    713012 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    713012 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[900])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.