0cb61fc7e7| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 44.530s | 67.964ms | 1 | 50 | 2.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.400s | 76.578us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 3.040s | 158.636us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 38.590s | 7.538ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 16.110s | 636.306us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 4.040s | 423.897us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 3.040s | 158.636us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 16.110s | 636.306us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.680s | 12.555us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.890s | 168.302us | 5 | 5 | 100.00 |
| V1 | TOTAL | 66 | 115 | 57.39 | |||
| V2 | csb_read | spi_device_csb_read | 0.910s | 30.002us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.790s | 3.480us | 0 | 20 | 0.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.740s | 17.122us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 18.630s | 810.408us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 18.630s | 810.408us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 31.970s | 11.742ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.330s | 209.095us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.387m | 67.926ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 50.600s | 19.116ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 40.070s | 14.901ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 40.070s | 14.901ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 47.090s | 21.817ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 47.090s | 21.817ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 47.090s | 21.817ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 47.090s | 21.817ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 47.090s | 21.817ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 41.650s | 141.316ms | 38 | 50 | 76.00 |
| V2 | mailbox_command | spi_device_mailbox | 3.419m | 93.411ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 3.419m | 93.411ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 3.419m | 93.411ms | 46 | 50 | 92.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 2.117m | 10.023ms | 42 | 50 | 84.00 |
| spi_device_read_buffer_direct | 17.450s | 1.703ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 3.419m | 93.411ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 1.050m | 9.091ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 35.110s | 15.546ms | 27 | 50 | 54.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 35.110s | 15.546ms | 27 | 50 | 54.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 44.530s | 67.964ms | 1 | 50 | 2.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 35.830s | 2.609ms | 1 | 50 | 2.00 |
| V2 | stress_all | spi_device_stress_all | 25.670s | 22.879ms | 14 | 50 | 28.00 |
| V2 | alert_test | spi_device_alert_test | 0.780s | 82.408us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.800s | 21.000us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.330s | 620.841us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 5.330s | 620.841us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.400s | 76.578us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 3.040s | 158.636us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 16.110s | 636.306us | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 5.350s | 208.985us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.400s | 76.578us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 3.040s | 158.636us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 16.110s | 636.306us | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 5.350s | 208.985us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 755 | 961 | 78.56 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.200s | 91.897us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 22.600s | 857.579us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 22.600s | 857.579us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 846 | 1101 | 76.84 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 13 | 59.09 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.13 | 97.55 | 92.89 | 98.61 | 80.85 | 95.99 | 90.94 | 88.08 |
Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 201 failures:
0.spi_device_flash_and_tpm.84676641021275945818037434115151748462418107629066204755914105396139319382733
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:e92aea73-57cc-4bf6-9296-6b18317595ae
1.spi_device_flash_and_tpm.41263527364810404526793882863867373969306376251119749204338898890437655975363
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:2d23f349-1f95-4d4b-8d26-6ddb22276e99
... and 47 more failures.
0.spi_device_flash_and_tpm_min_idle.81510385841054836660231701648312072031920155317977933456863963084275474477528
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:28623407-ee35-4a5b-b874-429ce529dc61
2.spi_device_flash_and_tpm_min_idle.64343880014421311278516667010259058516091397802049636251346442873220565436469
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:78bb0c0c-aa7a-48bc-944f-109e845a07e0
... and 43 more failures.
0.spi_device_stress_all.110968598078436546046149340253384514039253367838069587786678296413787716692357
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest/run.log
Job ID: smart:128e8a80-902d-4fe4-9c2b-45dcde78028b
1.spi_device_stress_all.54127439477674013498082218198016964567648345658540977655296955151757653094021
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest/run.log
Job ID: smart:5ba2d183-35b4-402d-b856-ebda0a7c3244
... and 31 more failures.
1.spi_device_cfg_cmd.11460992225780107092843276276982051694989143931990916540068328927603301681647
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
Job ID: smart:4bf452ea-2af7-40e0-8b75-3cb2be488d81
2.spi_device_cfg_cmd.16783213124182026057578392966564047576298210004779802786997079071587040285585
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest/run.log
Job ID: smart:8df60159-9604-4b9a-9ad1-12510bacf504
... and 13 more failures.
1.spi_device_flash_all.77070434408086876125997117484376811339089768841731608591614070138947885561634
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:9ce6acdc-d71e-4a24-a5f5-165e80f8801d
3.spi_device_flash_all.16999541501499751451538641460761443413850154599704921779763926063050104622067
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest/run.log
Job ID: smart:eced8474-7296-4d01-8f7b-febfe2071015
... and 41 more failures.
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
0.spi_device_mem_parity.50288941874226249227815453072695793397377760417911170415073461207069000512099
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 1065116 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[100])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1065116 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1065116 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[996])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.36972381422247881677921046794266016149659181910174508222836699015763685178305
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 1633637 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[92])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1633637 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1633637 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[988])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 16 failures:
0.spi_device_cfg_cmd.7706771607897006550778793042851486792593498608046312086119293320253266689815
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 265842324 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5f5aea) != exp '{'{other_status:'h17d6ba, wel:'h0, busy:'h0}, '{other_status:'h17d6ba, wel:'h0, busy:'h0}}
UVM_ERROR @ 266903540 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5f5aea) != exp '{'{other_status:'h17d6ba, wel:'h0, busy:'h0}, '{other_status:'h17d6ba, wel:'h0, busy:'h0}}
UVM_ERROR @ 268046388 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5f5aea) != exp '{'{other_status:'h17d6ba, wel:'h0, busy:'h0}, '{other_status:'h17d6ba, wel:'h0, busy:'h0}}
UVM_ERROR @ 268352508 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5f5aea) != exp '{'{other_status:'h17d6ba, wel:'h0, busy:'h0}, '{other_status:'h17d6ba, wel:'h0, busy:'h0}}
UVM_ERROR @ 268515772 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5f5aea) != exp '{'{other_status:'h17d6ba, wel:'h0, busy:'h0}, '{other_status:'h17d6ba, wel:'h0, busy:'h0}}
34.spi_device_cfg_cmd.111481289643765537759616739794302437225116342092035202055698070234819718489818
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 690757665 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 692979885 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 756090933 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 761090933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
1.spi_device_flash_and_tpm_min_idle.96715646918438163241920657602136191112682594859478355503318598075504708669926
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 911278059 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 913704277 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 913704277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_device_flash_and_tpm_min_idle.91538842194711644502734937639464817867579726557057575372161590175675658861106
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 1627507939 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 2100695439 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc913d2) != exp '{'{other_status:'h3244f4, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3244f4, wel:'h0, busy:'h0}, '{other_status:'h3244f4, wel:'h0, busy:'h0}}
UVM_ERROR @ 2112749439 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3244f4, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 2113249439 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3244f4, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 2113749439 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3244f4, wel:'h0, busy:'h0}} ) pred=0x0
... and 1 more failures.
18.spi_device_upload.73694365506247053136476294302467158715601315579498373835279529131386738840648
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest/run.log
UVM_ERROR @ 48155377835 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 48260806301 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 48276421143 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 7, test op = 0xb
UVM_INFO @ 58005755414 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 8, test op = 0xc7
UVM_INFO @ 58024155681 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 9, test op = 0xbb
26.spi_device_upload.40341209622882487953723795813950664682166906877925088567151583721875147891661
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest/run.log
UVM_ERROR @ 25403451 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 28122288 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 28381403 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 1, test op = 0xe9
UVM_INFO @ 28766172 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0x2a
UVM_INFO @ 51107666 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x35
... and 5 more failures.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 14 failures:
0.spi_device_flash_all.50636985817099101481016414464522363984730980596209262091093485989279905550928
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
UVM_FATAL @ 108265501 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 108265501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_device_flash_all.53884465833279702223531883682378327566514073743690525962829857256414582959236
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest/run.log
UVM_FATAL @ 257802848 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 257802848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
3.spi_device_upload.111968175760595258627104933325274309624539249338724518948192723679945025590546
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest/run.log
UVM_FATAL @ 416011824 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 416011824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_device_upload.111991445051539755613269028897577789044036690607758327043094215461531420521324
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest/run.log
UVM_FATAL @ 125410235 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 125410235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
5.spi_device_stress_all.70803207552353920350885068616129282969825361970511437618196236703194999458684
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest/run.log
UVM_FATAL @ 22878521276 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 22878521276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_device_stress_all.92368652651979330063969022405979236051455204146608106759903536021533920642322
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest/run.log
UVM_FATAL @ 34266842 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 34266842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
28.spi_device_flash_and_tpm_min_idle.16268018247033357237946301866575266764478186099471945345279786459530995225393
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 481733088 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 481733088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 2 failures:
Test spi_device_cfg_cmd has 1 failures.
18.spi_device_cfg_cmd.58798512225681916723420522972890090608230793146446467581782635854231205102651
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 24445841 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'hfd9bc, wel:'h0, busy:'h0}}
UVM_ERROR @ 24612513 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3f66f2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'hfd9bc, wel:'h0, busy:'h0}, '{other_status:'hfd9bc, wel:'h0, busy:'h0}}
UVM_INFO @ 24862521 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0xb7
UVM_ERROR @ 25008359 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3f66f2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'hfd9bc, wel:'h0, busy:'h0}, '{other_status:'hfd9bc, wel:'h0, busy:'h0}}
UVM_ERROR @ 25404205 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3f66f2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'hfd9bc, wel:'h0, busy:'h0}, '{other_status:'hfd9bc, wel:'h0, busy:'h0}, '{other_status:'h1caece, wel:'h0, busy:'h0}}
Test spi_device_flash_all has 1 failures.
33.spi_device_flash_all.88593952867870811800536028867573889243489912628402190574779635650119899708962
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest/run.log
UVM_ERROR @ 30800200 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xd54355) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3550d5, wel:'h0, busy:'h0}, '{other_status:'h3550d5, wel:'h0, busy:'h0}}
UVM_FATAL @ 32279415 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 32279415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:969) scoreboard [scoreboard] WEL mismatch: act=*, pred_fuzzy_q ('{}) pred=* has 1 failures:
2.spi_device_flash_all.30945949018377269319430990313164423710913361535134362470878588985166292401420
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest/run.log
UVM_ERROR @ 371595828 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 371687780 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 371779732 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 371871684 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 371963636 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
45.spi_device_cfg_cmd.80142700762317369759033424591322563126852936897543864692743399777345963477161
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 1414221329 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe78ea6) != exp '{'{other_status:'h39e3a9, wel:'h0, busy:'h0}, '{other_status:'h189f73, wel:'h0, busy:'h0}, '{other_status:'h39e3a9, wel:'h0, busy:'h0}, '{other_status:'h39e3a9, wel:'h0, busy:'h0}}
UVM_ERROR @ 1414976425 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe78ea6) != exp '{'{other_status:'h39e3a9, wel:'h0, busy:'h0}, '{other_status:'h189f73, wel:'h0, busy:'h0}, '{other_status:'h39e3a9, wel:'h0, busy:'h0}, '{other_status:'h39e3a9, wel:'h0, busy:'h0}}
UVM_ERROR @ 1415445809 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe78ea6) != exp '{'{other_status:'h39e3a9, wel:'h0, busy:'h0}, '{other_status:'h189f73, wel:'h0, busy:'h0}, '{other_status:'h39e3a9, wel:'h0, busy:'h0}, '{other_status:'h39e3a9, wel:'h0, busy:'h0}}
UVM_ERROR @ 1415833561 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe78ea6) != exp '{'{other_status:'h39e3a9, wel:'h0, busy:'h0}, '{other_status:'h189f73, wel:'h0, busy:'h0}, '{other_status:'h39e3a9, wel:'h0, busy:'h0}, '{other_status:'h39e3a9, wel:'h0, busy:'h0}}
UVM_ERROR @ 1416017233 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe78ea6) != exp '{'{other_status:'h39e3a9, wel:'h0, busy:'h0}, '{other_status:'h189f73, wel:'h0, busy:'h0}, '{other_status:'h39e3a9, wel:'h0, busy:'h0}, '{other_status:'h39e3a9, wel:'h0, busy:'h0}}