18c8953cf1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 37.100s | 5.882ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.360s | 46.681us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.920s | 190.151us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 34.910s | 19.476ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 21.410s | 4.104ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 4.180s | 166.426us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.920s | 190.151us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 21.410s | 4.104ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.680s | 12.305us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 2.130s | 57.429us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.880s | 59.466us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.810s | 1.157us | 0 | 20 | 0.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.760s | 31.294us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 10.340s | 662.476us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 10.340s | 662.476us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 38.790s | 13.056ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.190s | 199.464us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.025m | 49.392ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 37.230s | 14.130ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 40.290s | 53.553ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 40.290s | 53.553ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 46.310s | 40.222ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 46.310s | 40.222ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 46.310s | 40.222ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 46.310s | 40.222ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 46.310s | 40.222ms | 43 | 50 | 86.00 |
| spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 39.320s | 13.704ms | 31 | 50 | 62.00 |
| V2 | mailbox_command | spi_device_mailbox | 3.089m | 86.639ms | 44 | 50 | 88.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 3.089m | 86.639ms | 44 | 50 | 88.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 3.089m | 86.639ms | 44 | 50 | 88.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 3.177m | 48.887ms | 45 | 50 | 90.00 |
| spi_device_read_buffer_direct | 21.290s | 1.783ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 3.089m | 86.639ms | 44 | 50 | 88.00 |
| spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 18.080s | 10.372ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 41.730s | 5.093ms | 23 | 50 | 46.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 41.730s | 5.093ms | 23 | 50 | 46.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 37.100s | 5.882ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 1.101m | 12.767ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 32.610s | 3.059ms | 13 | 50 | 26.00 |
| V2 | alert_test | spi_device_alert_test | 0.790s | 53.896us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.810s | 32.946us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 4.460s | 710.290us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 4.460s | 710.290us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.360s | 46.681us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.920s | 190.151us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 21.410s | 4.104ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.140s | 466.036us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.360s | 46.681us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.920s | 190.151us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 21.410s | 4.104ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.140s | 466.036us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 740 | 961 | 77.00 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.140s | 184.766us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 22.780s | 898.522us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 22.780s | 898.522us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 830 | 1101 | 75.39 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 13 | 59.09 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.09 | 97.49 | 92.82 | 98.61 | 80.85 | 95.87 | 90.94 | 88.03 |
Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 204 failures:
0.spi_device_flash_all.94429130079728600471650983040109784269404735995707363174415193228957162741439
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:37b3b1f0-1682-45b7-b969-db0a38c26dfb
1.spi_device_flash_all.41897101388659895280658306184615376444440393588363390135169856021557027227313
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:69064716-61d4-45e6-a6c7-ae15d0f7925b
... and 43 more failures.
0.spi_device_flash_and_tpm.114706961767403830882674273066088804901452193083587208795959812359803230098015
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:f58d79de-9e33-4700-8f88-37ebb51b5dc1
1.spi_device_flash_and_tpm.9933335304204284917871597350093318158871827065860970852288644425118891478502
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:22356740-13a1-408d-a7c4-1ab9d5211926
... and 47 more failures.
0.spi_device_flash_and_tpm_min_idle.102757741089946025482961628905695013969320434830372822718896691934270096135874
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:c617f2ca-62e6-4b3c-9985-a66af0910b54
1.spi_device_flash_and_tpm_min_idle.37793330217544469575514707158554406257961349789336860799862944590744288644018
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:01954df7-552f-4027-a533-99f80baea932
... and 42 more failures.
1.spi_device_stress_all.70921192863060212574746697135528814161952401169037578195728411192238555359378
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest/run.log
Job ID: smart:9062780b-4051-45d3-b8f7-d257db02adf3
2.spi_device_stress_all.105843775996662186607551371462068877145794326865152657567092855485337356641321
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest/run.log
Job ID: smart:536d5a87-2d78-46f4-92dd-c1d155425975
... and 30 more failures.
4.spi_device_mailbox.105439895499245761723623902631207390480185378046921334251379353414998706686061
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest/run.log
Job ID: smart:0f4a3fa2-b4d4-4ad0-9850-b8c8f239c0ce
17.spi_device_mailbox.68717984493881650671312927232041555903226275585502465937319802479510007711408
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest/run.log
Job ID: smart:545ba24a-c78e-4c9c-afe1-d13c2781ca23
... and 4 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 28 failures:
Test spi_device_upload has 14 failures.
2.spi_device_upload.85580988996752207396977347773411976739220627190021678294794373952939085374819
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest/run.log
UVM_ERROR @ 115295589 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 165855589 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 166362839 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0x5
UVM_INFO @ 193409839 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 7, test op = 0xd4
UVM_INFO @ 193926839 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 8, test op = 0x44
9.spi_device_upload.84649892917479435484348838038297452857707654261091753598787937600598863487776
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest/run.log
UVM_ERROR @ 2538579569 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 4992139569 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 4997464569 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0xf8
UVM_INFO @ 6320569569 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0xb
UVM_INFO @ 7123564569 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0x94
... and 12 more failures.
Test spi_device_cfg_cmd has 11 failures.
3.spi_device_cfg_cmd.18091737921290739747954364744891254141332638084459421301249173241215858101973
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 1022773612 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1a205a) != exp '{'{other_status:'h68816, wel:'h0, busy:'h0}, '{other_status:'h68816, wel:'h0, busy:'h0}}
UVM_ERROR @ 1023173612 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1a205a) != exp '{'{other_status:'h68816, wel:'h0, busy:'h0}, '{other_status:'h68816, wel:'h0, busy:'h0}}
UVM_ERROR @ 1026413612 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1a205a) != exp '{'{other_status:'h68816, wel:'h0, busy:'h0}, '{other_status:'h68816, wel:'h0, busy:'h0}}
UVM_INFO @ 1027013612 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0xb7
UVM_ERROR @ 1027333612 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1a205a) != exp '{'{other_status:'h68816, wel:'h0, busy:'h0}, '{other_status:'h68816, wel:'h0, busy:'h0}}
15.spi_device_cfg_cmd.7682813102963751720009947678858672298257792225605620785007432109369127049880
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 266315346 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 267857025 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 268773699 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0x4
UVM_INFO @ 272690397 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 4, test op = 0xb7
UVM_INFO @ 275690421 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 5, test op = 0xb7
... and 9 more failures.
Test spi_device_flash_all has 2 failures.
5.spi_device_flash_all.92461053166308760390606288304238732914879709804979564432109035173096400772364
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest/run.log
UVM_ERROR @ 627707584 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5fe3b1) != exp '{'{other_status:'h17f8ec, wel:'h0, busy:'h0}, '{other_status:'h17f8ec, wel:'h0, busy:'h0}}
UVM_ERROR @ 889460592 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x37c5a5) != exp '{'{other_status:'hdf169, wel:'h0, busy:'h0}, '{other_status:'hdf169, wel:'h0, busy:'h0}}
UVM_INFO @ 955780216 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 1/16
UVM_ERROR @ 1193314724 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h193370, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 1193477988 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h193370, wel:'h0, busy:'h0}} ) pred=0x0
25.spi_device_flash_all.30600068445709888938078397589803612978520253760549327456091214798106980344324
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest/run.log
UVM_ERROR @ 147541005 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x154402) != exp '{'{other_status:'h55100, wel:'h0, busy:'h0}, '{other_status:'h55100, wel:'h0, busy:'h0}}
UVM_ERROR @ 148661005 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x154402) != exp '{'{other_status:'h55100, wel:'h0, busy:'h0}, '{other_status:'h55100, wel:'h0, busy:'h0}}
UVM_ERROR @ 149941005 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x154402) != exp '{'{other_status:'h55100, wel:'h0, busy:'h0}, '{other_status:'h55100, wel:'h0, busy:'h0}, '{other_status:'h367cda, wel:'h0, busy:'h0}}
UVM_INFO @ 182261005 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 1/5
UVM_ERROR @ 227041005 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xd9f36a) != exp '{'{other_status:'h367cda, wel:'h0, busy:'h0}, '{other_status:'h55100, wel:'h0, busy:'h0}, '{other_status:'h367cda, wel:'h0, busy:'h0}, '{other_status:'h367cda, wel:'h0, busy:'h0}}
Test spi_device_stress_all has 1 failures.
29.spi_device_stress_all.29077961817964274753349633742028177723726124717930877100369452578303030255636
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest/run.log
UVM_ERROR @ 71696794 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 102700233 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 102700233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
0.spi_device_mem_parity.70049916780405804823926283591750432636082975039499288021310817263412782230398
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 969617 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[99])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 969617 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 969617 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[995])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.47121474887798080683605241566559874352231828871439808152058077459471561693315
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 971670 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[110])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 971670 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 971670 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1006])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 17 failures:
Test spi_device_upload has 5 failures.
3.spi_device_upload.29444626787533678676292506188593567689709808550317968819177897834378433535214
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest/run.log
UVM_FATAL @ 190287605 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 190287605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_device_upload.89374267138973153602298696281719696603594384193669985512780825623756825515876
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest/run.log
UVM_FATAL @ 1874233257 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1874233257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_device_stress_all has 4 failures.
3.spi_device_stress_all.92937728564944924387497435834248497338396609356452531394195554439002678864029
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest/run.log
UVM_FATAL @ 241515125 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 241515125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_device_stress_all.57481809395663715612358906307794052605750280773763323451249972137384894208039
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest/run.log
UVM_FATAL @ 1504209353 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1504209353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_flash_all has 1 failures.
9.spi_device_flash_all.92066672702553131712817598429781618797432520021424647987355267011479585446286
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest/run.log
UVM_FATAL @ 10372397725 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10372397725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm_min_idle has 6 failures.
10.spi_device_flash_and_tpm_min_idle.111311349849209957884870873072990446575023721540850091799639520381225781373192
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 333113867 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 333113867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_device_flash_and_tpm_min_idle.43516746328948367162868357491973144146206878689811519916911588163234378863126
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 12766583749 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12766583749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_device_flash_and_tpm has 1 failures.
26.spi_device_flash_and_tpm.40942976775831879009107372585830207221495813389447418640404330544620368325056
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 5882448912 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5882448912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:969) scoreboard [scoreboard] WEL mismatch: act=*, pred_fuzzy_q ('{'{other_status:*, wel:*, busy:*}} ) pred=* has 1 failures:
7.spi_device_flash_all.70786343752848840335255761208830860619049561950706208919911452771886416082843
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest/run.log
UVM_ERROR @ 674567272 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3eb8c8, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 674930904 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3eb8c8, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 675294536 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3eb8c8, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 675658168 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3eb8c8, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 676021800 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3eb8c8, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
15.spi_device_flash_all.86462585077568000817999295358272650175460228209462172251215565037750016951918
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest/run.log
UVM_ERROR @ 168378703 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xefbed2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3befb4, wel:'h0, busy:'h0}, '{other_status:'h3befb4, wel:'h0, busy:'h0}}
UVM_ERROR @ 168459502 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3befb4, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 168499902 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3befb4, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 168540302 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3befb4, wel:'h0, busy:'h0}} ) pred=0x0
UVM_ERROR @ 168580702 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h3befb4, wel:'h0, busy:'h0}} ) pred=0x0