ecd9f08747| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 3.304m | 26.809ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.160s | 19.617us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.800s | 110.522us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 26.520s | 5.818ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 16.160s | 3.599ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.920s | 162.014us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.800s | 110.522us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 16.160s | 3.599ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.660s | 104.537us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.730s | 77.538us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.870s | 53.494us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.790s | 1.262us | 0 | 20 | 0.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.730s | 108.709us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 17.190s | 657.871us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 17.190s | 657.871us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 30.600s | 27.891ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.170s | 219.041us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.222m | 94.832ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 34.500s | 24.283ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 44.050s | 60.358ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 44.050s | 60.358ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 |
| V2 | cmd_read_status | spi_device_intercept | 58.310s | 6.020ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 58.310s | 6.020ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 58.310s | 6.020ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 58.310s | 6.020ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 58.310s | 6.020ms | 45 | 50 | 90.00 |
| spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 35.600s | 122.686ms | 37 | 50 | 74.00 |
| V2 | mailbox_command | spi_device_mailbox | 2.299m | 14.893ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 2.299m | 14.893ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 2.299m | 14.893ms | 46 | 50 | 92.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 1.726m | 15.012ms | 44 | 50 | 88.00 |
| spi_device_read_buffer_direct | 20.160s | 1.780ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 2.299m | 14.893ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 | ||
| V2 | quad_spi | spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 |
| V2 | dual_spi | spi_device_flash_all | 28.370s | 25.371ms | 1 | 50 | 2.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 35.710s | 39.041ms | 25 | 50 | 50.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 35.710s | 39.041ms | 25 | 50 | 50.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 3.304m | 26.809ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 27.240s | 5.348ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 52.600s | 10.165ms | 9 | 50 | 18.00 |
| V2 | alert_test | spi_device_alert_test | 0.810s | 13.687us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.800s | 171.239us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 4.800s | 74.758us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 4.800s | 74.758us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.160s | 19.617us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.800s | 110.522us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 16.160s | 3.599ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 3.970s | 477.359us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.160s | 19.617us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.800s | 110.522us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 16.160s | 3.599ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 3.970s | 477.359us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 748 | 961 | 77.84 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.010s | 398.925us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 24.200s | 1.137ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 24.200s | 1.137ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 838 | 1101 | 76.11 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 13 | 59.09 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.17 | 97.51 | 92.83 | 98.61 | 80.85 | 95.90 | 90.94 | 88.58 |
Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 206 failures:
0.spi_device_flash_all.14952450197335089172781679198799954388683880525877084031882178491424968374697
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:42facf99-21b8-4f18-9246-7e0251d4f428
1.spi_device_flash_all.61303939155850294490078587878829271440324029003836093684292386310816923041978
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:9c964474-6ee5-4f47-807b-bc782810a948
... and 45 more failures.
0.spi_device_flash_and_tpm.16303914434499991893723371382734329559589617088085302941522169501120047439284
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:5c00f2b1-6762-4fd7-ba6c-8ffec46721ea
1.spi_device_flash_and_tpm.104807201911234988890767016048217240094738144985420122030995623455510459908556
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
Job ID: smart:5829b5e8-0a61-4378-9924-b39344afb780
... and 43 more failures.
0.spi_device_flash_and_tpm_min_idle.39641426481591028160352638873588167388953273621492479370403340285844581251470
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:062aca1e-6027-4943-8da6-a9e1f18da15f
1.spi_device_flash_and_tpm_min_idle.29619876569698089203635202562488130139774339645035078449402238721402823510247
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:333d19bd-0f05-4f03-b312-8e24cd6f46af
... and 42 more failures.
0.spi_device_stress_all.18939934531783738192681451184584598891831698202329608225382500196950740123190
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest/run.log
Job ID: smart:60df71c1-4d41-46b4-9b4b-553433afc6a6
3.spi_device_stress_all.5803029380753347936050317896961424690236970179851052367801658733442715756222
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest/run.log
Job ID: smart:750dc560-0276-4abc-bb5d-29c97e9aa52b
... and 35 more failures.
1.spi_device_intercept.107274683215086343390399042820930994110071335589322792990737258268124687639469
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest/run.log
Job ID: smart:93bc0903-0b9d-4e32-8213-ed87a550cf53
4.spi_device_intercept.77135399904236917614263305965287812657344166438482705157704859345125518469947
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest/run.log
Job ID: smart:1bd9190f-357f-4219-bd2c-25e2fd676685
... and 3 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 23 failures:
Test spi_device_cfg_cmd has 6 failures.
2.spi_device_cfg_cmd.81978129501999013055899555199885367906597995241622259976898722324526644779298
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 26497014 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcce1ee) != exp '{'{other_status:'h33387b, wel:'h0, busy:'h0}, '{other_status:'h33387b, wel:'h0, busy:'h0}}
UVM_ERROR @ 26667014 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcce1ee) != exp '{'{other_status:'h33387b, wel:'h0, busy:'h0}, '{other_status:'h33387b, wel:'h0, busy:'h0}}
UVM_ERROR @ 27137014 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcce1ee) != exp '{'{other_status:'h33387b, wel:'h0, busy:'h0}, '{other_status:'h33387b, wel:'h0, busy:'h0}}
UVM_ERROR @ 27197014 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcce1ee) != exp '{'{other_status:'h33387b, wel:'h0, busy:'h0}, '{other_status:'h33387b, wel:'h0, busy:'h0}}
UVM_ERROR @ 27347014 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcce1ee) != exp '{'{other_status:'h33387b, wel:'h0, busy:'h0}, '{other_status:'h33387b, wel:'h0, busy:'h0}}
4.spi_device_cfg_cmd.98888947071777900224777484497142370416711382279089756586079135703890386325267
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 747676615 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2c3c76) != exp '{'{other_status:'hb0f1d, wel:'h0, busy:'h0}, '{other_status:'hb0f1d, wel:'h0, busy:'h0}}
UVM_ERROR @ 749516615 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2c3c76) != exp '{'{other_status:'hb0f1d, wel:'h0, busy:'h0}, '{other_status:'hb0f1d, wel:'h0, busy:'h0}}
UVM_ERROR @ 749716615 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2c3c76) != exp '{'{other_status:'hb0f1d, wel:'h0, busy:'h0}, '{other_status:'hb0f1d, wel:'h0, busy:'h0}}
UVM_ERROR @ 750196615 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2c3c76) != exp '{'{other_status:'hb0f1d, wel:'h0, busy:'h0}, '{other_status:'hb0f1d, wel:'h0, busy:'h0}}
UVM_INFO @ 751036615 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0xb7
... and 4 more failures.
Test spi_device_upload has 9 failures.
6.spi_device_upload.29813143458887641846923591904397988556971603523380419035262636963573676386906
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest/run.log
UVM_ERROR @ 1024759471 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 1518991686 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 1523433001 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x11
UVM_INFO @ 3633655376 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0xb8
UVM_INFO @ 6048526886 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0x39
18.spi_device_upload.79271359537560071475713270363271477167819006286225323126095907773885434546875
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest/run.log
UVM_ERROR @ 75343423 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 123584550 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 124836531 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0xb7
UVM_INFO @ 125661648 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x3b
UVM_INFO @ 130043090 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0x5a
... and 7 more failures.
Test spi_device_flash_and_tpm_min_idle has 4 failures.
11.spi_device_flash_and_tpm_min_idle.15687995957718370423946905411920884623648615629896406324718253593442260226353
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 5300401773 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 5348124690 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5348124690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_device_flash_and_tpm_min_idle.12649346758665969703104727126708728547258019583694468804607668347254988825240
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 71143273 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 90393889 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 325213903 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 419602340 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1f42d5, wel:'h0, busy:'h0}}
UVM_FATAL @ 426051179 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
... and 2 more failures.
Test spi_device_flash_and_tpm has 2 failures.
18.spi_device_flash_and_tpm.30204473411826478301632746418847840199273487354274238809571784831964917612118
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 3941413527 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 10430438675 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/2
UVM_INFO @ 14829897389 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/9
UVM_ERROR @ 17298212811 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x79837d) != exp '{'{other_status:'h1e60df, wel:'h0, busy:'h0}, '{other_status:'h1e60df, wel:'h0, busy:'h0}}
UVM_ERROR @ 19278637607 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x79837d) != exp '{'{other_status:'h1e60df, wel:'h0, busy:'h0}, '{other_status:'h1e60df, wel:'h0, busy:'h0}}
43.spi_device_flash_and_tpm.60004701479006595350184660437660858082888206784093422466740671864640436406108
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 254851682 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x48b979) != exp '{'{other_status:'h122e5e, wel:'h0, busy:'h0}, '{other_status:'h122e5e, wel:'h0, busy:'h0}}
UVM_FATAL @ 255974473 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 255974473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_all has 2 failures.
23.spi_device_flash_all.28679340494819534296651267470011868099930958742663731996058207852855697414284
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest/run.log
UVM_ERROR @ 595196853 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 1210384823 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 1211839383 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 1213293943 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 1214748503 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
48.spi_device_flash_all.59124244826955062179709489922876692770948382931145529825248600300901149693918
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest/run.log
UVM_ERROR @ 6907252607 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 6928329509 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 20198470085 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 1/16
UVM_FATAL @ 25371195666 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25371195666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
0.spi_device_mem_parity.76633710293933174707363946351780668894368910095058087647937603844386882165337
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 880366 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[80])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 880366 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 880366 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[976])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.83464089458137981774035043673934895302071767036528011675809326582933686287464
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 1805294 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[52])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1805294 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1805294 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[948])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 13 failures:
2.spi_device_stress_all.67295774935429806382926215160744795139028732594360633409614972352043599957527
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest/run.log
UVM_FATAL @ 90641982 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 90641982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_device_stress_all.71437035509484962817086014746131807562178854065779036323026114964717153692288
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest/run.log
UVM_FATAL @ 41588770 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 41588770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
5.spi_device_flash_and_tpm.111520303764406424293182604507204984862239485161812446703648668499468558853259
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 102340879 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 102340879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_device_flash_and_tpm.43455364371771825142497525598173922381359945634386777597360040704688302006667
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 567629937 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 567629937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
17.spi_device_upload.31869197971483729706633038970271384851200358807983020328245775818046164914621
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest/run.log
UVM_FATAL @ 405503600 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 405503600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_device_upload.77633498048549580297341973370136377188718320695243296008738600531605102049112
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest/run.log
UVM_FATAL @ 1736347833 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1736347833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
41.spi_device_flash_and_tpm_min_idle.37013415690969694961029793618022552354933307427800076472955065033768585016734
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 50445286 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 50445286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.spi_device_flash_and_tpm_min_idle.52936591541020894277853309374954368296859174865837465142202437821243140402287
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 691742740 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 691742740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
17.spi_device_cfg_cmd.114483708473466977080840434443727794263799225369196170529721043314350317522072
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 100884601 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5c3a) != exp '{'{other_status:'h170e, wel:'h0, busy:'h0}, '{other_status:'h170e, wel:'h0, busy:'h0}, '{other_status:'h79362, wel:'h0, busy:'h0}}
UVM_ERROR @ 101244601 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5c3a) != exp '{'{other_status:'h170e, wel:'h0, busy:'h0}, '{other_status:'h170e, wel:'h0, busy:'h0}, '{other_status:'h79362, wel:'h0, busy:'h0}}
UVM_ERROR @ 101474601 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5c3a) != exp '{'{other_status:'h170e, wel:'h0, busy:'h0}, '{other_status:'h170e, wel:'h0, busy:'h0}, '{other_status:'h79362, wel:'h0, busy:'h0}}
UVM_ERROR @ 101634601 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1e4d8a) != exp '{'{other_status:'h170e, wel:'h0, busy:'h0}, '{other_status:'h79362, wel:'h0, busy:'h0}, '{other_status:'h79362, wel:'h0, busy:'h0}}
UVM_INFO @ 101834601 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0x4