d0c52cdadd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 42.870s | 14.161ms | 0 | 50 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.420s | 125.181us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.880s | 520.094us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 23.690s | 3.330ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 20.490s | 1.296ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 3.910s | 663.910us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.880s | 520.094us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 20.490s | 1.296ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.660s | 17.090us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 2.430s | 137.173us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | csb_read | spi_device_csb_read | 0.820s | 53.534us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.740s | 1.965us | 0 | 20 | 0.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.730s | 73.924us | 1 | 1 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 12.080s | 474.167us | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 12.080s | 474.167us | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 34.560s | 42.613ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.200s | 114.742us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.296m | 31.887ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 55.290s | 20.380ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 48.400s | 16.247ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 48.400s | 16.247ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 58.180s | 22.152ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 58.180s | 22.152ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 58.180s | 22.152ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 58.180s | 22.152ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 58.180s | 22.152ms | 42 | 50 | 84.00 |
| spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 51.580s | 88.701ms | 37 | 50 | 74.00 |
| V2 | mailbox_command | spi_device_mailbox | 3.197m | 131.547ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 3.197m | 131.547ms | 46 | 50 | 92.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 3.197m | 131.547ms | 46 | 50 | 92.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 4.162m | 97.065ms | 46 | 50 | 92.00 |
| spi_device_read_buffer_direct | 19.250s | 4.903ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 3.197m | 131.547ms | 46 | 50 | 92.00 |
| spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 22.710s | 4.359ms | 0 | 50 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 32.600s | 7.739ms | 21 | 50 | 42.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 32.600s | 7.739ms | 21 | 50 | 42.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 42.870s | 14.161ms | 0 | 50 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 35.420s | 14.413ms | 0 | 50 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 12.370s | 865.266us | 11 | 50 | 22.00 |
| V2 | alert_test | spi_device_alert_test | 0.790s | 14.797us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.820s | 48.366us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.270s | 82.757us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 5.270s | 82.757us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.420s | 125.181us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.880s | 520.094us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 20.490s | 1.296ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.080s | 204.752us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.420s | 125.181us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.880s | 520.094us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 20.490s | 1.296ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 4.080s | 204.752us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 744 | 961 | 77.42 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.190s | 309.379us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 23.630s | 12.083ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 23.630s | 12.083ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 834 | 1101 | 75.75 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 13 | 59.09 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.12 | 97.61 | 92.93 | 98.61 | 80.85 | 96.01 | 90.94 | 87.88 |
Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 199 failures:
0.spi_device_cfg_cmd.45125008875784202045661559554089582596158421068352710459768078265673327587012
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
Job ID: smart:972042e8-ebc7-47dd-bfe7-55ccba816fa6
1.spi_device_cfg_cmd.75477072339640344612434472319050773378382025095407367098094026908678921378515
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
Job ID: smart:1cfb787c-e927-415b-8af0-21409678870c
... and 16 more failures.
0.spi_device_flash_all.14487308903790393027357987377148432868720555925301694840702886964068870750526
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log
Job ID: smart:2e54d840-44c6-496a-abee-6d3f33aacb09
1.spi_device_flash_all.8023313264453963157452562995239412774766409675912312669693061142760576886877
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log
Job ID: smart:5f983a01-62e5-49d5-855e-d34fbfb0b629
... and 42 more failures.
0.spi_device_flash_and_tpm_min_idle.16089169759069613289684575440614163559691076485618125292056739878990276670693
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:f6d43c04-c487-4242-9d83-552531fc799d
1.spi_device_flash_and_tpm_min_idle.42462319916935681362180300323034931850024549622420580628584781284306539088440
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
Job ID: smart:630cdf0c-85a3-4c18-aa01-2e9674521b84
... and 42 more failures.
0.spi_device_stress_all.46786215615409200013937081044380799769812950663225400434959191788286039202401
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest/run.log
Job ID: smart:b978ab98-202f-4fd2-8230-373ccf4eb31b
1.spi_device_stress_all.34235555798734038255642156249711488476897706822494420050592434500382764336937
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest/run.log
Job ID: smart:67a15a6a-f907-4c41-95dc-345d829ddc7a
... and 33 more failures.
1.spi_device_mailbox.17978597595845384093576430888551511660619826158078045658297798460040502234417
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest/run.log
Job ID: smart:6106b8e5-56a2-4fb6-ae8e-8a1348911b36
13.spi_device_mailbox.2838941474504939617775704589235129530269494179492779310207925533869509644818
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest/run.log
Job ID: smart:26ad25ba-f43f-4122-a076-c834a49073c0
... and 2 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 23 failures:
Test spi_device_flash_and_tpm_min_idle has 4 failures.
2.spi_device_flash_and_tpm_min_idle.26713908597883920719360176213711798040490077423779840272935847072924288003654
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 57800444 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 62273994 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 121826216 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 121868312 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
UVM_ERROR @ 121910408 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{}) pred=0x0
26.spi_device_flash_and_tpm_min_idle.9530522428986303116267680464383769658702659432694019115043512760779734758690
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 2103756265 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 2110066266 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2110066266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_device_cfg_cmd has 7 failures.
3.spi_device_cfg_cmd.21203753829381972664456987560959562155507960011178338623842708599901173293395
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 300291373 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xd4a7f2) != exp '{'{other_status:'h3529fc, wel:'h0, busy:'h0}, '{other_status:'h3529fc, wel:'h0, busy:'h0}}
UVM_INFO @ 300834222 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 9, test op = 0xb7
UVM_ERROR @ 301291358 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xd4a7f2) != exp '{'{other_status:'h3529fc, wel:'h0, busy:'h0}, '{other_status:'h3529fc, wel:'h0, busy:'h0}}
UVM_ERROR @ 302719908 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xd4a7f2) != exp '{'{other_status:'h3529fc, wel:'h0, busy:'h0}, '{other_status:'h3529fc, wel:'h0, busy:'h0}, '{other_status:'h31fa47, wel:'h0, busy:'h0}}
UVM_INFO @ 303091331 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 10, test op = 0xe9
9.spi_device_cfg_cmd.18473830469416853959847837431774859631118918480323921457687789395431700456773
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 2598280147 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x67283a) != exp '{'{other_status:'h19ca0e, wel:'h0, busy:'h0}, '{other_status:'h19ca0e, wel:'h0, busy:'h0}}
UVM_ERROR @ 2600371054 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x67283a) != exp '{'{other_status:'h19ca0e, wel:'h0, busy:'h0}, '{other_status:'h19ca0e, wel:'h0, busy:'h0}}
UVM_ERROR @ 2605825594 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x67283a) != exp '{'{other_status:'h19ca0e, wel:'h0, busy:'h0}, '{other_status:'h19ca0e, wel:'h0, busy:'h0}, '{other_status:'h1ace8f, wel:'h0, busy:'h0}}
UVM_ERROR @ 2607007411 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x67283a) != exp '{'{other_status:'h19ca0e, wel:'h0, busy:'h0}, '{other_status:'h1ace8f, wel:'h0, busy:'h0}, '{other_status:'h1ace8f, wel:'h0, busy:'h0}}
UVM_ERROR @ 2608098319 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6b3a3e) != exp '{'{other_status:'h19ca0e, wel:'h0, busy:'h0}, '{other_status:'h1ace8f, wel:'h0, busy:'h0}, '{other_status:'h1ace8f, wel:'h0, busy:'h0}}
... and 5 more failures.
Test spi_device_stress_all has 2 failures.
7.spi_device_stress_all.106009197657859486743541923836016376080658082916646206456384483574065071609830
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest/run.log
UVM_ERROR @ 114121097 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 170039553 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 170310395 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 188343521 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 188343521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
20.spi_device_stress_all.96256000404597452747237699890048729340673290956445710472611551559546992977711
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest/run.log
UVM_ERROR @ 1135325206 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 1286705207 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1286705207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_upload has 7 failures.
8.spi_device_upload.25258209593258666047318878195611602320074401759375141489003373214707352147395
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest/run.log
UVM_ERROR @ 161702597 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 163094312 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 163789112 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0xed
UVM_INFO @ 170104432 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0x74
UVM_INFO @ 191784336 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 6, test op = 0x60
12.spi_device_upload.9301485584250021251405590753600535059832244975961652078053869326158379685906
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest/run.log
UVM_ERROR @ 2580978282 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 2687773346 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_INFO @ 2692973734 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0x1e
UVM_INFO @ 2707997654 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0x6f
UVM_INFO @ 3881580122 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 5, test op = 0x6
... and 5 more failures.
Test spi_device_flash_all has 1 failures.
32.spi_device_flash_all.35731122154756672616750830281742081493258399248310113815203327285223771372397
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest/run.log
UVM_ERROR @ 3367007140 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL @ 3378647141 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3378647141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 21 failures:
Test spi_device_flash_and_tpm has 6 failures.
0.spi_device_flash_and_tpm.23240774072219235263405547659956809345367478387092338543431274973993410701414
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 245016935 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 245016935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_device_flash_and_tpm.108976631173667570111237802282564619487918716932468159341248238235459378431486
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 61500255070 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 61500255070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_device_upload has 6 failures.
4.spi_device_upload.86685920192040224934336400702705860646467786180983759805927486463796576312442
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest/run.log
UVM_FATAL @ 164905879 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 164905879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_device_upload.114830353205207982407509883673668222875738642656801369681528665180339131453953
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest/run.log
UVM_FATAL @ 128439911 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 128439911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_device_flash_and_tpm_min_idle has 2 failures.
8.spi_device_flash_and_tpm_min_idle.70478846135354723373602855034636160346350983564482043953510389210314638742479
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 287308311 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 287308311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.spi_device_flash_and_tpm_min_idle.27318297232856643319073477442311785730418665736189177043625015571387654631209
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 518417076 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 518417076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_all has 5 failures.
20.spi_device_flash_all.21326289566047627713329752233004043908118712548678144399538570180499091124332
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest/run.log
UVM_FATAL @ 7028678705 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7028678705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.spi_device_flash_all.26590913783667285824733706706159405567644813551828764122442026446522053136310
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest/run.log
UVM_FATAL @ 3926968837 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3926968837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_device_stress_all has 2 failures.
34.spi_device_stress_all.43126148945228062875026673867774353503400810335693209445902960009773456616571
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest/run.log
UVM_FATAL @ 1974761765 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1974761765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_device_stress_all.70143532213680729900365418241046442643854591464079203259293808623537280868582
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest/run.log
UVM_FATAL @ 865266334 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 865266334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
0.spi_device_mem_parity.87655476205479582577875777496962805094331384781042443113921214059058361209790
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 925339 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[76])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 925339 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 925339 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[972])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.66344865274459902433340361002880699387093140983332971771118869806879098118341
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 1338401 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[19])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1338401 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1338401 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[915])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 18 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 3 failures:
16.spi_device_cfg_cmd.112983058526014675400208254546924558612022658517764207563323590410098650804886
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 94821961 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xddcc8e) != exp '{'{other_status:'h95f4f, wel:'h0, busy:'h0}, '{other_status:'h377323, wel:'h0, busy:'h0}, '{other_status:'h377323, wel:'h0, busy:'h0}}
UVM_ERROR @ 95655301 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xddcc8e) != exp '{'{other_status:'h95f4f, wel:'h0, busy:'h0}, '{other_status:'h377323, wel:'h0, busy:'h0}, '{other_status:'h377323, wel:'h0, busy:'h0}}
UVM_ERROR @ 97071979 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xddcc8e) != exp '{'{other_status:'h95f4f, wel:'h0, busy:'h0}, '{other_status:'h377323, wel:'h0, busy:'h0}, '{other_status:'h377323, wel:'h0, busy:'h0}}
UVM_ERROR @ 97280314 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xddcc8e) != exp '{'{other_status:'h95f4f, wel:'h0, busy:'h0}, '{other_status:'h377323, wel:'h0, busy:'h0}, '{other_status:'h377323, wel:'h0, busy:'h0}}
UVM_ERROR @ 97738651 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xddcc8e) != exp '{'{other_status:'h95f4f, wel:'h0, busy:'h0}, '{other_status:'h377323, wel:'h0, busy:'h0}, '{other_status:'h377323, wel:'h0, busy:'h0}}
39.spi_device_cfg_cmd.8639982047503219154834077248818632997362298735486476541675972412188866793144
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 96609584 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xecec3e) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3b3b0f, wel:'h0, busy:'h0}, '{other_status:'h3b3b0f, wel:'h0, busy:'h0}}
UVM_ERROR @ 98449584 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xecec3e) != exp '{'{other_status:'h3b3b0f, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3b3b0f, wel:'h0, busy:'h0}, '{other_status:'h3b3b0f, wel:'h0, busy:'h0}}
UVM_ERROR @ 99049584 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xecec3e) != exp '{'{other_status:'h3b3b0f, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3b3b0f, wel:'h0, busy:'h0}, '{other_status:'h3b3b0f, wel:'h0, busy:'h0}}
UVM_ERROR @ 99449584 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xecec3e) != exp '{'{other_status:'h3b3b0f, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3b3b0f, wel:'h0, busy:'h0}, '{other_status:'h3b3b0f, wel:'h0, busy:'h0}}
UVM_ERROR @ 100129584 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xecec3e) != exp '{'{other_status:'h3b3b0f, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3b3b0f, wel:'h0, busy:'h0}, '{other_status:'h3b3b0f, wel:'h0, busy:'h0}}
... and 1 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
22.spi_device_cfg_cmd.74461580971124394673733386586557135974748126829442371937951679129653549785300
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 119573260 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6ee93a) != exp '{'{other_status:'h18033c, wel:'h0, busy:'h0}, '{other_status:'h65e69, wel:'h0, busy:'h0}, '{other_status:'h1bba4e, wel:'h0, busy:'h0}, '{other_status:'h1bba4e, wel:'h0, busy:'h0}}
UVM_ERROR @ 138653260 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6ee93a) != exp '{'{other_status:'h18033c, wel:'h0, busy:'h0}, '{other_status:'h65e69, wel:'h0, busy:'h0}, '{other_status:'h1bba4e, wel:'h0, busy:'h0}, '{other_status:'h1bba4e, wel:'h0, busy:'h0}}
UVM_INFO @ 143653260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---