SPI_DEVICE/1R1W Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.409m	156.654ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.470s	92.687us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.990s	485.691us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.280s	7.493ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.660s	318.660us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.910s	518.691us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.990s	485.691us	20	20	100.00
		spi_device_csr_aliasing	21.660s	318.660us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	162.467us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.350s	76.425us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.910s	15.075us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	1.584us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	16.522us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.260s	238.027us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.260s	238.027us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.930s	32.333ms	50	50	100.00
		spi_device_tpm_sts_read	1.110s	241.462us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	59.490s	11.820ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.410s	9.600ms	50	50	100.00
		spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	22.340s	16.976ms	50	50	100.00
		spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	22.340s	16.976ms	50	50	100.00
		spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	31.700s	7.836ms	50	50	100.00
		spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	31.700s	7.836ms	50	50	100.00
		spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	31.700s	7.836ms	50	50	100.00
		spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	31.700s	7.836ms	50	50	100.00
		spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	31.700s	7.836ms	50	50	100.00
		spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	49.750s	298.841ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.686m	98.511ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.686m	98.511ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.686m	98.511ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.091m	16.964ms	50	50	100.00
		spi_device_read_buffer_direct	18.080s	5.660ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.686m	98.511ms	50	50	100.00
		spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.180m	72.049ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.770s	4.057ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	33.770s	4.057ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.409m	156.654ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.441m	62.484ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.663m	364.693ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.840s	44.061us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	24.854us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.800s	235.585us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.800s	235.585us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.470s	92.687us	5	5	100.00
		spi_device_csr_rw	2.990s	485.691us	20	20	100.00
		spi_device_csr_aliasing	21.660s	318.660us	5	5	100.00
		spi_device_same_csr_outstanding	3.970s	2.619ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.470s	92.687us	5	5	100.00
		spi_device_csr_rw	2.990s	485.691us	20	20	100.00
		spi_device_csr_aliasing	21.660s	318.660us	5	5	100.00
		spi_device_same_csr_outstanding	3.970s	2.619ms	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.230s	255.844us	5	5	100.00
		spi_device_tl_intg_err	23.800s	3.173ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.800s	3.173ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.91	98.29	94.11	98.61	89.36	97.04	95.83	98.17

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.47820906976213930690898196752307378363637887990471727449933148349341552520504
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2819636 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[86])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2819636 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2819636 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[982])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.14575120864188529056015450172056162380990410433351589964575400237059686917897
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   5007082 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[48])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   5007082 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   5007082 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[944])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.