SPI_DEVICE/1R1W Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.806m	60.294ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.430s	44.860us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.050s	91.592us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.420s	4.838ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.840s	1.256ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.090s	229.383us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.050s	91.592us	20	20	100.00
		spi_device_csr_aliasing	15.840s	1.256ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.660s	15.343us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.380s	129.589us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	19.991us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	12.211us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	31.091us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.570s	948.812us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.570s	948.812us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	29.020s	9.525ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	99.766us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	50.760s	10.134ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	24.150s	29.805ms	50	50	100.00
		spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	51.110s	18.228ms	50	50	100.00
		spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	51.110s	18.228ms	50	50	100.00
		spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	21.230s	4.908ms	50	50	100.00
		spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	21.230s	4.908ms	50	50	100.00
		spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	21.230s	4.908ms	50	50	100.00
		spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	21.230s	4.908ms	50	50	100.00
		spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	21.230s	4.908ms	50	50	100.00
		spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.070s	26.665ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.891m	47.162ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.891m	47.162ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.891m	47.162ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.583m	31.220ms	50	50	100.00
		spi_device_read_buffer_direct	16.180s	7.071ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.891m	47.162ms	50	50	100.00
		spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.859m	75.429ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	18.100s	7.597ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	18.100s	7.597ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.806m	60.294ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.037m	268.347ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.560m	80.401ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	45.125us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	50.290us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.620s	382.782us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.620s	382.782us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.430s	44.860us	5	5	100.00
		spi_device_csr_rw	3.050s	91.592us	20	20	100.00
		spi_device_csr_aliasing	15.840s	1.256ms	5	5	100.00
		spi_device_same_csr_outstanding	4.430s	278.089us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.430s	44.860us	5	5	100.00
		spi_device_csr_rw	3.050s	91.592us	20	20	100.00
		spi_device_csr_aliasing	15.840s	1.256ms	5	5	100.00
		spi_device_same_csr_outstanding	4.430s	278.089us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.220s	81.856us	5	5	100.00
		spi_device_tl_intg_err	25.640s	4.441ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.640s	4.441ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.93	98.30	94.12	98.61	89.36	97.06	95.83	98.22

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.65383221405251827465704356710245043244435307541085734795137313064866922860654
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3637632 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[72])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3637632 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3637632 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[968])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.109712110395013967621742052586425409908816753281334238411263601633699548729749
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1117812 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[85])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1117812 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1117812 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[981])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.