SPI_DEVICE/1R1W Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.157m	315.050ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.210s	42.083us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.010s	782.213us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.030s	20.154ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.460s	1.051ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.030s	310.986us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.010s	782.213us	20	20	100.00
		spi_device_csr_aliasing	22.460s	1.051ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	12.762us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.590s	133.815us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	17.843us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.780s	1.101us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	29.004us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.540s	479.304us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.540s	479.304us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.750s	9.177ms	50	50	100.00
		spi_device_tpm_sts_read	1.110s	139.935us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	59.570s	11.828ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.580s	37.335ms	50	50	100.00
		spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	28.590s	10.918ms	50	50	100.00
		spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	28.590s	10.918ms	50	50	100.00
		spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.940s	7.676ms	50	50	100.00
		spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.940s	7.676ms	50	50	100.00
		spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.940s	7.676ms	50	50	100.00
		spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.940s	7.676ms	50	50	100.00
		spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.940s	7.676ms	50	50	100.00
		spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	26.920s	6.672ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.186m	26.614ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.186m	26.614ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.186m	26.614ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	48.690s	4.507ms	50	50	100.00
		spi_device_read_buffer_direct	20.400s	4.012ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.186m	26.614ms	50	50	100.00
		spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.394m	57.946ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	14.960s	1.428ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	14.960s	1.428ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.157m	315.050ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.878m	81.053ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.769m	406.324ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	20.044us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	38.330us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.490s	175.687us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.490s	175.687us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.210s	42.083us	5	5	100.00
		spi_device_csr_rw	3.010s	782.213us	20	20	100.00
		spi_device_csr_aliasing	22.460s	1.051ms	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	705.220us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.210s	42.083us	5	5	100.00
		spi_device_csr_rw	3.010s	782.213us	20	20	100.00
		spi_device_csr_aliasing	22.460s	1.051ms	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	705.220us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.240s	374.385us	5	5	100.00
		spi_device_tl_intg_err	24.100s	3.440ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.100s	3.440ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.93	98.30	94.11	98.61	89.36	97.06	95.83	98.22

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.31371412067392006096381552854982912658370671522394841770900925311768058910470
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1984376 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[19])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1984376 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1984376 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[915])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.25005204826044432091655671584486911462850768582243326884589689852625981601564
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1111632 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[68])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1111632 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1111632 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[964])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.