SPI_DEVICE/1R1W Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.382m	150.261ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.250s	33.373us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.880s	39.208us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.140s	1.887ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.890s	7.649ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.100s	417.461us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.880s	39.208us	20	20	100.00
		spi_device_csr_aliasing	25.890s	7.649ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	13.605us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.200s	26.788us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.840s	59.251us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.730s	1.042us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	15.328us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.230s	211.444us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.230s	211.444us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.330s	8.372ms	50	50	100.00
		spi_device_tpm_sts_read	1.160s	114.956us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	56.350s	18.980ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.350s	58.943ms	50	50	100.00
		spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	32.830s	44.657ms	50	50	100.00
		spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	32.830s	44.657ms	50	50	100.00
		spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.200s	2.765ms	50	50	100.00
		spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.200s	2.765ms	50	50	100.00
		spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.200s	2.765ms	50	50	100.00
		spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.200s	2.765ms	50	50	100.00
		spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.200s	2.765ms	50	50	100.00
		spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.730s	11.159ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.815m	26.508ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.815m	26.508ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.815m	26.508ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.339m	18.545ms	50	50	100.00
		spi_device_read_buffer_direct	17.250s	10.803ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.815m	26.508ms	50	50	100.00
		spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.209m	45.655ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	20.390s	20.426ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	20.390s	20.426ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.382m	150.261ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.472m	83.101ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.290m	143.117ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	160.354us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	13.375us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.610s	928.116us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.610s	928.116us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.250s	33.373us	5	5	100.00
		spi_device_csr_rw	2.880s	39.208us	20	20	100.00
		spi_device_csr_aliasing	25.890s	7.649ms	5	5	100.00
		spi_device_same_csr_outstanding	4.780s	209.701us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.250s	33.373us	5	5	100.00
		spi_device_csr_rw	2.880s	39.208us	20	20	100.00
		spi_device_csr_aliasing	25.890s	7.649ms	5	5	100.00
		spi_device_same_csr_outstanding	4.780s	209.701us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.210s	504.242us	5	5	100.00
		spi_device_tl_intg_err	23.840s	7.375ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.840s	7.375ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1080	1101	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	98.30	94.11	98.61	89.36	97.14	95.84	99.20

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.59883175982245272400152621862959000052897879720262470516415264930606563182436
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1025157 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[17])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1025157 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1025157 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[913])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.62016157265009351434539017712332029640398099906934781044622981559760535433268
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    931116 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[110])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    931116 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    931116 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1006])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.addr_mode' is being accessed

has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

38.spi_device_flash_and_tpm.76638460467097162174153455815754791698190442879505629115992104484323559881131
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 11807198662 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.addr_mode' is being accessed
  UVM_INFO @ 15381118482 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/3
  UVM_INFO @ 15693282977 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/8
  UVM_INFO @ 21441385912 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/8
  UVM_INFO @ 22979446747 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/8