SPI_DEVICE/1R1W Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.107m	55.280ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.230s	34.986us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.830s	454.950us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.360s	3.061ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.970s	1.087ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.130s	1.005ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.830s	454.950us	20	20	100.00
		spi_device_csr_aliasing	23.970s	1.087ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	13.735us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.330s	360.819us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	21.962us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.780s	1.107us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	16.224us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.870s	284.438us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.870s	284.438us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.520s	10.137ms	50	50	100.00
		spi_device_tpm_sts_read	1.030s	102.017us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.770s	8.115ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	24.690s	24.849ms	50	50	100.00
		spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	23.810s	79.566ms	50	50	100.00
		spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	23.810s	79.566ms	50	50	100.00
		spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	32.930s	3.271ms	50	50	100.00
		spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	32.930s	3.271ms	50	50	100.00
		spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	32.930s	3.271ms	50	50	100.00
		spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	32.930s	3.271ms	50	50	100.00
		spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	32.930s	3.271ms	50	50	100.00
		spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	50.790s	30.309ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.594m	33.993ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.594m	33.993ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.594m	33.993ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.207m	4.005ms	50	50	100.00
		spi_device_read_buffer_direct	20.000s	1.290ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.594m	33.993ms	50	50	100.00
		spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.019m	46.296ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	34.370s	28.540ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	34.370s	28.540ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.107m	55.280ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.676m	179.900ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.219m	122.967ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	41.612us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	16.401us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.130s	194.772us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.130s	194.772us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.230s	34.986us	5	5	100.00
		spi_device_csr_rw	2.830s	454.950us	20	20	100.00
		spi_device_csr_aliasing	23.970s	1.087ms	5	5	100.00
		spi_device_same_csr_outstanding	4.270s	154.211us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.230s	34.986us	5	5	100.00
		spi_device_csr_rw	2.830s	454.950us	20	20	100.00
		spi_device_csr_aliasing	23.970s	1.087ms	5	5	100.00
		spi_device_same_csr_outstanding	4.270s	154.211us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.260s	168.698us	5	5	100.00
		spi_device_tl_intg_err	22.410s	1.975ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.410s	1.975ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1081	1101	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.100185771410005580761390512557948205987489734585603403120690615084709167766119
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    802032 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[104])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    802032 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    802032 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1000])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.59739336565194306120907540887693229391242870184949034753066819960746970406378
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2640977 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[88])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2640977 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2640977 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[984])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = *:Bad Gateway has 1 failures:
- Test spi_device has 1 failures.
  - cov_report
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/cov_report/cov_report.log