SPI_DEVICE/1R1W Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.611m	465.101ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	74.712us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.730s	878.240us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.720s	9.417ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.150s	1.240ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.990s	1.025ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.730s	878.240us	20	20	100.00
		spi_device_csr_aliasing	16.150s	1.240ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.730s	170.640us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.130s	292.717us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.860s	21.606us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	1.065us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	16.448us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	4.220s	455.430us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	4.220s	455.430us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.300s	9.708ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	483.545us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	45.500s	15.824ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	18.950s	6.530ms	50	50	100.00
		spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.170s	111.199ms	50	50	100.00
		spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.170s	111.199ms	50	50	100.00
		spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	34.600s	3.357ms	50	50	100.00
		spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	34.600s	3.357ms	50	50	100.00
		spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.600s	3.357ms	50	50	100.00
		spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	34.600s	3.357ms	50	50	100.00
		spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.600s	3.357ms	50	50	100.00
		spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	52.010s	30.155ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.620m	8.485ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.620m	8.485ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.620m	8.485ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.239m	5.712ms	50	50	100.00
		spi_device_read_buffer_direct	19.570s	5.892ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.620m	8.485ms	50	50	100.00
		spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.596m	55.177ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.150s	5.040ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.150s	5.040ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.611m	465.101ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.268m	1.054s	50	50	100.00
V2	stress_all	spi_device_stress_all	13.228m	89.810ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	200.047us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	19.475us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.500s	147.237us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.500s	147.237us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	74.712us	5	5	100.00
		spi_device_csr_rw	2.730s	878.240us	20	20	100.00
		spi_device_csr_aliasing	16.150s	1.240ms	5	5	100.00
		spi_device_same_csr_outstanding	4.960s	231.152us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	74.712us	5	5	100.00
		spi_device_csr_rw	2.730s	878.240us	20	20	100.00
		spi_device_csr_aliasing	16.150s	1.240ms	5	5	100.00
		spi_device_same_csr_outstanding	4.960s	231.152us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.800s	410.528us	5	5	100.00
		spi_device_tl_intg_err	23.910s	1.988ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.910s	1.988ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.327m	922.942ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.34446772875126559113293610372260933922180035499936176222369215106743238225642
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2479317 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[50])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2479317 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2479317 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[946])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.59547863728294833174538439196540113694624901207957582778683265937971499684355
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    977933 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[99])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    977933 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    977933 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[995])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.