SPI_DEVICE/1R1W Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.861m	60.237ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.600s	173.369us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.810s	87.296us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.460s	7.205ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.870s	2.420ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.240s	920.225us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.810s	87.296us	20	20	100.00
		spi_device_csr_aliasing	15.870s	2.420ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	13.774us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.300s	271.872us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	22.667us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	3.194us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	43.406us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.700s	270.173us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.700s	270.173us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.430s	38.323ms	50	50	100.00
		spi_device_tpm_sts_read	1.090s	143.703us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	58.660s	44.986ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	33.970s	54.213ms	50	50	100.00
		spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.940s	40.443ms	50	50	100.00
		spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.940s	40.443ms	50	50	100.00
		spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.990s	16.654ms	50	50	100.00
		spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.990s	16.654ms	50	50	100.00
		spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.990s	16.654ms	50	50	100.00
		spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.990s	16.654ms	50	50	100.00
		spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.990s	16.654ms	50	50	100.00
		spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	52.000s	15.879ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.294m	78.016ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.294m	78.016ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.294m	78.016ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.377m	23.960ms	50	50	100.00
		spi_device_read_buffer_direct	20.810s	6.973ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.294m	78.016ms	50	50	100.00
		spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.536m	112.806ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.980s	11.367ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.980s	11.367ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.861m	60.237ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.881m	155.935ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.589m	351.915ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.810s	39.318us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	14.342us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.650s	69.092us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.650s	69.092us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.600s	173.369us	5	5	100.00
		spi_device_csr_rw	2.810s	87.296us	20	20	100.00
		spi_device_csr_aliasing	15.870s	2.420ms	5	5	100.00
		spi_device_same_csr_outstanding	4.170s	727.600us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.600s	173.369us	5	5	100.00
		spi_device_csr_rw	2.810s	87.296us	20	20	100.00
		spi_device_csr_aliasing	15.870s	2.420ms	5	5	100.00
		spi_device_same_csr_outstanding	4.170s	727.600us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.260s	326.895us	5	5	100.00
		spi_device_tl_intg_err	23.030s	4.081ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.030s	4.081ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.326m	343.699ms	48	50	96.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.28480720145729137083831792160619283136834667989442589468895036533212142002132
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   9345850 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[31])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   9345850 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   9345850 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[927])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.71782041099640174624350158623561805320222372589433123703905823410847744717935
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1138118 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[97])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1138118 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1138118 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[993])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 31.spi_device_flash_mode_ignore_cmds.108603760806914211188896405066643664886936590793677280786109420258922229964226
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:540524e1-933c-4265-8f63-11d2a7062e96
```

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

37.spi_device_flash_mode_ignore_cmds.62307985442075635126521895624146905594495238784351672302673169944677712709053
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 25780338835 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 25998135606 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 7/9
  UVM_INFO @ 25998135606 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 8/9
  UVM_INFO @ 30255341246 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 8/9
  UVM_INFO @ 30305443593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]