SPI_DEVICE/1R1W Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.858m	273.090ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	26.749us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.610s	178.474us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.260s	20.111ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.220s	1.852ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.300s	117.877us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.610s	178.474us	20	20	100.00
		spi_device_csr_aliasing	23.220s	1.852ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	16.483us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.310s	224.306us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.880s	19.758us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	2.628us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	22.070us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.460s	150.854us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.460s	150.854us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	26.100s	8.948ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	276.832us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.090s	19.498ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	34.240s	46.315ms	50	50	100.00
		spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.260s	15.112ms	50	50	100.00
		spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.260s	15.112ms	50	50	100.00
		spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	41.230s	32.405ms	50	50	100.00
		spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	41.230s	32.405ms	50	50	100.00
		spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	41.230s	32.405ms	50	50	100.00
		spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	41.230s	32.405ms	50	50	100.00
		spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	41.230s	32.405ms	50	50	100.00
		spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.660s	57.472ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.924m	61.897ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.924m	61.897ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.924m	61.897ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	58.770s	5.265ms	50	50	100.00
		spi_device_read_buffer_direct	17.330s	5.567ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.924m	61.897ms	50	50	100.00
		spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.829m	151.334ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	41.700s	4.339ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	41.700s	4.339ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.858m	273.090ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.449m	62.267ms	50	50	100.00
V2	stress_all	spi_device_stress_all	10.440m	517.544ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	16.209us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	44.033us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.680s	876.947us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.680s	876.947us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	26.749us	5	5	100.00
		spi_device_csr_rw	2.610s	178.474us	20	20	100.00
		spi_device_csr_aliasing	23.220s	1.852ms	5	5	100.00
		spi_device_same_csr_outstanding	4.590s	764.203us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	26.749us	5	5	100.00
		spi_device_csr_rw	2.610s	178.474us	20	20	100.00
		spi_device_csr_aliasing	23.220s	1.852ms	5	5	100.00
		spi_device_same_csr_outstanding	4.590s	764.203us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.110s	329.877us	5	5	100.00
		spi_device_tl_intg_err	22.510s	1.722ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.510s	1.722ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.356m	259.512ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	94.01	98.62	89.36	97.21	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.93954309211480147165695555920177388381008546768926800951083246707005211420563
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4209371 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[55])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4209371 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4209371 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[951])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.53950991773206343754635104416322393269974694784598034392105773178518984765708
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4325605 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[43])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4325605 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4325605 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[939])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.