SPI_DEVICE/1R1W Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.049m	989.298ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	87.381us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.940s	446.368us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	40.440s	11.787ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.170s	1.817ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.030s	325.205us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.940s	446.368us	20	20	100.00
		spi_device_csr_aliasing	24.170s	1.817ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	10.889us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.160s	29.401us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.920s	38.137us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	1.487us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	17.428us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.210s	307.608us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.210s	307.608us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.140s	8.715ms	50	50	100.00
		spi_device_tpm_sts_read	1.080s	478.131us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	56.700s	11.624ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	36.870s	103.817ms	50	50	100.00
		spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	21.620s	9.257ms	50	50	100.00
		spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	21.620s	9.257ms	50	50	100.00
		spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	44.450s	3.946ms	50	50	100.00
		spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	44.450s	3.946ms	50	50	100.00
		spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	44.450s	3.946ms	50	50	100.00
		spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	44.450s	3.946ms	50	50	100.00
		spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	44.450s	3.946ms	50	50	100.00
		spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	26.490s	6.539ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.732m	13.140ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.732m	13.140ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.732m	13.140ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.519m	30.652ms	50	50	100.00
		spi_device_read_buffer_direct	20.340s	3.530ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.732m	13.140ms	50	50	100.00
		spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.963m	45.303ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	30.500s	6.613ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	30.500s	6.613ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.049m	989.298ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.804m	61.238ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.880m	469.768ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	11.460us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	11.382us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.870s	416.428us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.870s	416.428us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	87.381us	5	5	100.00
		spi_device_csr_rw	2.940s	446.368us	20	20	100.00
		spi_device_csr_aliasing	24.170s	1.817ms	5	5	100.00
		spi_device_same_csr_outstanding	4.700s	316.762us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	87.381us	5	5	100.00
		spi_device_csr_rw	2.940s	446.368us	20	20	100.00
		spi_device_csr_aliasing	24.170s	1.817ms	5	5	100.00
		spi_device_same_csr_outstanding	4.700s	316.762us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.270s	83.460us	5	5	100.00
		spi_device_tl_intg_err	23.580s	880.384us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.580s	880.384us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.970m	70.930ms	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.47296624444737373023582784856106201364412392748631236231969427600325110395653
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1110854 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[92])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1110854 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1110854 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[988])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.45645945209506962517847353833700502203070143289305152327506214901601978404241
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    897634 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[90])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    897634 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    897634 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[986])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_FATAL (spi_device_scoreboard.sv:989) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 32.spi_device_flash_mode_ignore_cmds.24530049160517965944020665130016928265255779274606648071541882982496313654457
    Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 861913702 ps: (spi_device_scoreboard.sv:989) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 861913702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```