SPI_DEVICE/1R1W Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.596m	320.718ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	228.427us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.000s	130.762us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.050s	7.843ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.900s	2.283ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.220s	163.026us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.000s	130.762us	20	20	100.00
		spi_device_csr_aliasing	22.900s	2.283ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	13.424us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.990s	29.506us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	21.495us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.730s	7.069us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.770s	18.667us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.450s	200.498us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.450s	200.498us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	19.600s	31.739ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	317.288us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	42.360s	113.477ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	27.880s	9.612ms	50	50	100.00
		spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	35.500s	89.081ms	50	50	100.00
		spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	35.500s	89.081ms	50	50	100.00
		spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.260s	18.547ms	50	50	100.00
		spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.260s	18.547ms	50	50	100.00
		spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.260s	18.547ms	50	50	100.00
		spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.260s	18.547ms	50	50	100.00
		spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.260s	18.547ms	50	50	100.00
		spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	31.010s	23.048ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.277m	238.479ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.277m	238.479ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.277m	238.479ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.207m	12.757ms	50	50	100.00
		spi_device_read_buffer_direct	21.470s	2.304ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.277m	238.479ms	50	50	100.00
		spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.857m	149.933ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	31.960s	13.563ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	31.960s	13.563ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.596m	320.718ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.532m	191.897ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.257m	101.729ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	16.116us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.860s	18.220us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.200s	661.242us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.200s	661.242us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	228.427us	5	5	100.00
		spi_device_csr_rw	3.000s	130.762us	20	20	100.00
		spi_device_csr_aliasing	22.900s	2.283ms	5	5	100.00
		spi_device_same_csr_outstanding	4.790s	905.638us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	228.427us	5	5	100.00
		spi_device_csr_rw	3.000s	130.762us	20	20	100.00
		spi_device_csr_aliasing	22.900s	2.283ms	5	5	100.00
		spi_device_same_csr_outstanding	4.790s	905.638us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.050s	192.807us	5	5	100.00
		spi_device_tl_intg_err	24.100s	5.163ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.100s	5.163ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.216m	135.934ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	94.02	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.3402962142081853472569246243912540406740207401608453858827349582325595081821
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2418344 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[11])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2418344 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2418344 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[907])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.75892553300602709325780078355638471296207692516699552595746950430538467344949
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1249386 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[80])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1249386 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1249386 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[976])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.