SPI_DEVICE/1R1W Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.829m	92.784ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.380s	23.102us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.880s	183.875us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.010s	25.860ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.970s	4.767ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.060s	162.922us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.880s	183.875us	20	20	100.00
		spi_device_csr_aliasing	24.970s	4.767ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	11.026us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.210s	62.449us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	22.453us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.810s	5.792us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	15.842us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.540s	401.412us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.540s	401.412us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.120s	51.655ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	105.395us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.650s	8.589ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.580s	10.397ms	50	50	100.00
		spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	26.640s	110.380ms	50	50	100.00
		spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	26.640s	110.380ms	50	50	100.00
		spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.570s	11.318ms	50	50	100.00
		spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.570s	11.318ms	50	50	100.00
		spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.570s	11.318ms	50	50	100.00
		spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.570s	11.318ms	50	50	100.00
		spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.570s	11.318ms	50	50	100.00
		spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	26.000s	7.663ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.041m	93.182ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.041m	93.182ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.041m	93.182ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.011m	4.041ms	50	50	100.00
		spi_device_read_buffer_direct	21.680s	2.117ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.041m	93.182ms	50	50	100.00
		spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.429m	46.815ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	35.200s	3.444ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	35.200s	3.444ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.829m	92.784ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.737m	300.625ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.901m	469.548ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.820s	82.816us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	15.931us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.300s	68.441us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.300s	68.441us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.380s	23.102us	5	5	100.00
		spi_device_csr_rw	2.880s	183.875us	20	20	100.00
		spi_device_csr_aliasing	24.970s	4.767ms	5	5	100.00
		spi_device_same_csr_outstanding	4.480s	794.526us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.380s	23.102us	5	5	100.00
		spi_device_csr_rw	2.880s	183.875us	20	20	100.00
		spi_device_csr_aliasing	24.970s	4.767ms	5	5	100.00
		spi_device_same_csr_outstanding	4.480s	794.526us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.190s	177.956us	5	5	100.00
		spi_device_tl_intg_err	23.450s	1.650ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.450s	1.650ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.851m	1.129s	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	94.02	98.62	89.36	97.21	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.7217203920707742702924564571563067442241999204262286232692179915116429737860
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    761741 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[35])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    761741 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    761741 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[931])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.225582794412681064442828891978396074289712039710258148692097960532833399553
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4246913 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[75])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4246913 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4246913 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[971])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.