SPI_DEVICE/1R1W Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	16.365m	737.725ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	94.194us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.650s	79.302us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.300s	1.050ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.150s	5.065ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.140s	58.604us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.650s	79.302us	20	20	100.00
		spi_device_csr_aliasing	22.150s	5.065ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	12.029us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.160s	217.860us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	13.035us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	1.440us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	116.185us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	8.050s	482.450us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.050s	482.450us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.920s	8.487ms	50	50	100.00
		spi_device_tpm_sts_read	1.130s	211.344us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.120s	30.798ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.310s	45.559ms	50	50	100.00
		spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.270s	37.422ms	50	50	100.00
		spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.270s	37.422ms	50	50	100.00
		spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.170s	58.973ms	50	50	100.00
		spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.170s	58.973ms	50	50	100.00
		spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.170s	58.973ms	50	50	100.00
		spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.170s	58.973ms	50	50	100.00
		spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.170s	58.973ms	50	50	100.00
		spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	24.510s	5.223ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.219m	21.463ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.219m	21.463ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.219m	21.463ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.181m	4.620ms	50	50	100.00
		spi_device_read_buffer_direct	20.650s	26.501ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.219m	21.463ms	50	50	100.00
		spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.662m	74.898ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	34.290s	3.418ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	34.290s	3.418ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	16.365m	737.725ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.686m	111.620ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.127m	66.651ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.830s	109.081us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	27.307us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.930s	2.580ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.930s	2.580ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	94.194us	5	5	100.00
		spi_device_csr_rw	2.650s	79.302us	20	20	100.00
		spi_device_csr_aliasing	22.150s	5.065ms	5	5	100.00
		spi_device_same_csr_outstanding	4.740s	911.762us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	94.194us	5	5	100.00
		spi_device_csr_rw	2.650s	79.302us	20	20	100.00
		spi_device_csr_aliasing	22.150s	5.065ms	5	5	100.00
		spi_device_same_csr_outstanding	4.740s	911.762us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.140s	172.143us	5	5	100.00
		spi_device_tl_intg_err	18.610s	301.267us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.610s	301.267us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.941m	66.262ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.50955446337152995587334134253909972597724810507286917916083060577512072876209
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    799487 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[46])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    799487 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    799487 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[942])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.12103383576362619752079621571542563329330273910850956795451349833545854697983
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4123457 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[26])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4123457 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4123457 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[922])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.