SPI_DEVICE/1R1W Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.168m	327.703ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.360s	149.337us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.780s	112.706us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.690s	7.202ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.260s	947.997us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.310s	247.383us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.780s	112.706us	20	20	100.00
		spi_device_csr_aliasing	24.260s	947.997us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	13.054us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.140s	91.267us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.830s	17.141us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	1.063us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	24.528us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.110s	544.873us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.110s	544.873us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.960s	16.516ms	50	50	100.00
		spi_device_tpm_sts_read	1.110s	141.941us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	50.290s	19.565ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.610s	15.449ms	50	50	100.00
		spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	21.060s	6.485ms	50	50	100.00
		spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	21.060s	6.485ms	50	50	100.00
		spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	31.200s	15.254ms	50	50	100.00
		spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	31.200s	15.254ms	50	50	100.00
		spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	31.200s	15.254ms	50	50	100.00
		spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	31.200s	15.254ms	50	50	100.00
		spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	31.200s	15.254ms	50	50	100.00
		spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	27.560s	35.240ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.091m	14.312ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.091m	14.312ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.091m	14.312ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.289m	11.712ms	50	50	100.00
		spi_device_read_buffer_direct	27.160s	20.333ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.091m	14.312ms	50	50	100.00
		spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.871m	359.577ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	22.830s	4.416ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	22.830s	4.416ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.168m	327.703ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.219m	93.934ms	50	50	100.00
V2	stress_all	spi_device_stress_all	21.899m	152.043ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.770s	12.348us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	234.542us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.460s	1.440ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.460s	1.440ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.360s	149.337us	5	5	100.00
		spi_device_csr_rw	2.780s	112.706us	20	20	100.00
		spi_device_csr_aliasing	24.260s	947.997us	5	5	100.00
		spi_device_same_csr_outstanding	4.340s	318.807us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.360s	149.337us	5	5	100.00
		spi_device_csr_rw	2.780s	112.706us	20	20	100.00
		spi_device_csr_aliasing	24.260s	947.997us	5	5	100.00
		spi_device_same_csr_outstanding	4.340s	318.807us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.180s	304.012us	5	5	100.00
		spi_device_tl_intg_err	23.480s	2.026ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.480s	2.026ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.522m	152.456ms	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.43520213960200543224317621759668432143422143033097493659990424181191473965088
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    996688 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[34])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    996688 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    996688 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[930])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.58597741212747420558355218434296748701897915749442421626663240179874071116411
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @  13757168 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[99])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @  13757168 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @  13757168 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[995])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Job spi_device_1r1w-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 47.spi_device_flash_mode_ignore_cmds.91651342185860921517785211482554310929591015517275779100473426570837915877112
    Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job ID: smart:354bd0e8-38ae-47b5-864a-c3d71b4c12c8
```