SPI_DEVICE/1R1W Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.952m	235.050ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.280s	21.885us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.590s	76.487us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.410s	1.851ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.760s	855.235us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.190s	305.919us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.590s	76.487us	20	20	100.00
		spi_device_csr_aliasing	14.760s	855.235us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	11.941us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.070s	51.041us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	18.939us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.780s	10.781us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	16.448us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.970s	1.063ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.970s	1.063ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.250s	41.491ms	50	50	100.00
		spi_device_tpm_sts_read	1.060s	134.335us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	51.100s	20.431ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	32.940s	10.758ms	50	50	100.00
		spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.900s	13.494ms	50	50	100.00
		spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.900s	13.494ms	50	50	100.00
		spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.640s	5.839ms	50	50	100.00
		spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.640s	5.839ms	50	50	100.00
		spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.640s	5.839ms	50	50	100.00
		spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.640s	5.839ms	50	50	100.00
		spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.640s	5.839ms	50	50	100.00
		spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.880s	52.552ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.795m	128.297ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.795m	128.297ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.795m	128.297ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.471m	5.573ms	50	50	100.00
		spi_device_read_buffer_direct	19.820s	8.256ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.795m	128.297ms	50	50	100.00
		spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.103m	78.187ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.660s	8.101ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.660s	8.101ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.952m	235.050ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.267m	166.758ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.517m	393.362ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	43.628us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.920s	35.889us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.630s	87.199us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.630s	87.199us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.280s	21.885us	5	5	100.00
		spi_device_csr_rw	2.590s	76.487us	20	20	100.00
		spi_device_csr_aliasing	14.760s	855.235us	5	5	100.00
		spi_device_same_csr_outstanding	4.510s	762.069us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.280s	21.885us	5	5	100.00
		spi_device_csr_rw	2.590s	76.487us	20	20	100.00
		spi_device_csr_aliasing	14.760s	855.235us	5	5	100.00
		spi_device_same_csr_outstanding	4.510s	762.069us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.220s	161.136us	5	5	100.00
		spi_device_tl_intg_err	25.360s	4.364ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.360s	4.364ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.839m	114.085ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.9559786133062498288859632475259035500565843340636599333921571872674883731153
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4029020 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[17])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4029020 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4029020 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[913])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.10637086025984690738310829647581265898584851890991690598489964638830080651899
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @  17993914 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[45])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @  17993914 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @  17993914 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[941])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.