SPI_DEVICE/1R1W Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.974m	65.568ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.220s	79.101us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.150s	107.646us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	30.770s	8.203ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	13.920s	877.870us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.230s	518.934us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.150s	107.646us	20	20	100.00
		spi_device_csr_aliasing	13.920s	877.870us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.590s	10.188us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.930s	55.346us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.770s	40.259us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.720s	4.808us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	20.420us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	5.910s	764.332us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.910s	764.332us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.020s	44.755ms	50	50	100.00
		spi_device_tpm_sts_read	1.090s	165.611us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	32.880s	25.862ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	29.780s	36.064ms	50	50	100.00
		spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.210s	34.839ms	50	50	100.00
		spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.210s	34.839ms	50	50	100.00
		spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	23.630s	10.642ms	50	50	100.00
		spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	23.630s	10.642ms	50	50	100.00
		spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	23.630s	10.642ms	50	50	100.00
		spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	23.630s	10.642ms	50	50	100.00
		spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	23.630s	10.642ms	50	50	100.00
		spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	34.560s	45.553ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.436m	39.837ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.436m	39.837ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.436m	39.837ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.178m	5.743ms	50	50	100.00
		spi_device_read_buffer_direct	14.570s	6.716ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.436m	39.837ms	50	50	100.00
		spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.797m	265.562ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.880s	1.267ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.880s	1.267ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.974m	65.568ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.457m	229.951ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.472m	1.418s	50	50	100.00
V2	alert_test	spi_device_alert_test	0.740s	62.705us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.700s	12.113us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.310s	179.459us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.310s	179.459us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.220s	79.101us	5	5	100.00
		spi_device_csr_rw	2.150s	107.646us	20	20	100.00
		spi_device_csr_aliasing	13.920s	877.870us	5	5	100.00
		spi_device_same_csr_outstanding	3.680s	431.569us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.220s	79.101us	5	5	100.00
		spi_device_csr_rw	2.150s	107.646us	20	20	100.00
		spi_device_csr_aliasing	13.920s	877.870us	5	5	100.00
		spi_device_same_csr_outstanding	3.680s	431.569us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.210s	88.007us	5	5	100.00
		spi_device_tl_intg_err	20.250s	2.127ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.250s	2.127ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	30.549m	1.500s	49	50	98.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	7	87.50
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.61739313305280358831242046144085091621731994193532089541698287214863737917179
Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2124078 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[11])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2124078 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2124078 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[907])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.91310284616213927963810575206541472580766421266679254776492182364764197523642
Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   5396213 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[0])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   5396213 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   5396213 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[896])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1032) scoreboard [scoreboard] Compare failed, downstream item: has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

1.spi_device_flash_and_tpm.85885882427343654532025773156749666842913930774355580416015293943929641661084
Line 80, in log /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 6023931839 ps: (spi_device_scoreboard.sv:1032) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare failed, downstream item:
  -------------------------------------------------------------------------
  Name                               Type              Size  Value
  -------------------------------------------------------------------------
  host_item                          spi_item          -     @328587

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 30.spi_device_flash_mode_ignore_cmds.48174461075050796832150734575676499409076245876233146901282923571836580186663
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```