SPI_DEVICE/1R1W Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.226m	40.928ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.390s	67.834us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.490s	40.775us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.100s	588.531us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.390s	935.759us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.500s	148.744us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.490s	40.775us	20	20	100.00
		spi_device_csr_aliasing	20.390s	935.759us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.880s	16.975us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.060s	563.436us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.260s	20.602us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	4.374us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.050s	26.979us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.220s	976.188us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.220s	976.188us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	39.720s	49.228ms	50	50	100.00
		spi_device_tpm_sts_read	1.800s	138.576us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.193m	37.939ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	43.690s	15.485ms	50	50	100.00
		spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.161m	54.237ms	50	50	100.00
		spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.161m	54.237ms	50	50	100.00
		spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	36.630s	9.269ms	50	50	100.00
		spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	36.630s	9.269ms	50	50	100.00
		spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	36.630s	9.269ms	50	50	100.00
		spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	36.630s	9.269ms	50	50	100.00
		spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	36.630s	9.269ms	50	50	100.00
		spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.673m	69.305ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.251m	10.704ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.251m	10.704ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.251m	10.704ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.123m	2.795ms	50	50	100.00
		spi_device_read_buffer_direct	24.660s	1.607ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.251m	10.704ms	50	50	100.00
		spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.615m	271.799ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	31.210s	4.310ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	31.210s	4.310ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.226m	40.928ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	20.581m	92.271ms	50	50	100.00
V2	stress_all	spi_device_stress_all	22.718m	672.254ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.170s	19.469us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.160s	16.875us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.220s	235.555us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.220s	235.555us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.390s	67.834us	5	5	100.00
		spi_device_csr_rw	3.490s	40.775us	20	20	100.00
		spi_device_csr_aliasing	20.390s	935.759us	5	5	100.00
		spi_device_same_csr_outstanding	4.550s	245.179us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.390s	67.834us	5	5	100.00
		spi_device_csr_rw	3.490s	40.775us	20	20	100.00
		spi_device_csr_aliasing	20.390s	935.759us	5	5	100.00
		spi_device_same_csr_outstanding	4.550s	245.179us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.950s	643.839us	5	5	100.00
		spi_device_tl_intg_err	20.100s	2.128ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.100s	2.128ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	16.220m	83.454ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.90730249730913639451009696613477086403017204687327418813574173373558726904569
Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4154861 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[80])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4154861 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4154861 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[976])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.106092040774272819301157471077335368964324064472635258630689808155930177851574
Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   3190515 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[58])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   3190515 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   3190515 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[954])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.