SPI_DEVICE/1R1W Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.430m	305.139ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.010s	835.069us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.230s	371.734us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.300s	1.852ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.080s	6.972ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.420s	201.195us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.230s	371.734us	20	20	100.00
		spi_device_csr_aliasing	22.080s	6.972ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.990s	10.943us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.280s	120.131us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.260s	125.942us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	6.202us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.040s	46.977us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.220s	138.717us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.220s	138.717us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	34.090s	6.816ms	50	50	100.00
		spi_device_tpm_sts_read	1.740s	114.872us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	55.800s	28.364ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.123m	10.890ms	50	50	100.00
		spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	51.930s	94.271ms	50	50	100.00
		spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	51.930s	94.271ms	50	50	100.00
		spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	40.300s	6.944ms	50	50	100.00
		spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	40.300s	6.944ms	50	50	100.00
		spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	40.300s	6.944ms	50	50	100.00
		spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	40.300s	6.944ms	50	50	100.00
		spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	40.300s	6.944ms	50	50	100.00
		spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.198m	46.921ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.933m	48.659ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.933m	48.659ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.933m	48.659ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.085m	2.965ms	50	50	100.00
		spi_device_read_buffer_direct	28.250s	2.121ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.933m	48.659ms	50	50	100.00
		spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	13.772m	79.973ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	31.220s	2.654ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	31.220s	2.654ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.430m	305.139ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.054m	255.827ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.323m	111.026ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.170s	47.941us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.170s	62.086us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.910s	249.211us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.910s	249.211us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.010s	835.069us	5	5	100.00
		spi_device_csr_rw	3.230s	371.734us	20	20	100.00
		spi_device_csr_aliasing	22.080s	6.972ms	5	5	100.00
		spi_device_same_csr_outstanding	5.340s	311.111us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.010s	835.069us	5	5	100.00
		spi_device_csr_rw	3.230s	371.734us	20	20	100.00
		spi_device_csr_aliasing	22.080s	6.972ms	5	5	100.00
		spi_device_same_csr_outstanding	5.340s	311.111us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.890s	312.756us	5	5	100.00
		spi_device_tl_intg_err	22.480s	856.589us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.480s	856.589us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.577m	712.393ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	94.01	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.26493056143424056149534038604775532038427205255025999051359762771007603484013
Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   8277832 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[91])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   8277832 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   8277832 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[987])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.86383469744869384911301295420037879288602989985352253028116437368647433975106
Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1138286 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[36])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1138286 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1138286 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[932])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.