SPI_DEVICE/1R1W Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	16.189m	292.493ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.980s	292.615us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.590s	176.438us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	41.970s	1.049ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	29.140s	2.856ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.910s	61.296us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.590s	176.438us	20	20	100.00
		spi_device_csr_aliasing	29.140s	2.856ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.020s	16.393us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.230s	62.573us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.260s	170.874us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	14.625us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.140s	27.414us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	14.660s	256.193us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	14.660s	256.193us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	49.060s	33.652ms	50	50	100.00
		spi_device_tpm_sts_read	1.740s	257.221us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.135m	43.600ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.523m	60.641ms	50	50	100.00
		spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.002m	9.581ms	50	50	100.00
		spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.002m	9.581ms	50	50	100.00
		spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	1.167m	4.477ms	50	50	100.00
		spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	1.167m	4.477ms	50	50	100.00
		spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	1.167m	4.477ms	50	50	100.00
		spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	1.167m	4.477ms	50	50	100.00
		spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	1.167m	4.477ms	50	50	100.00
		spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.067m	39.351ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.215m	24.322ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.215m	24.322ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.215m	24.322ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	50.750s	2.583ms	50	50	100.00
		spi_device_read_buffer_direct	27.290s	1.746ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.215m	24.322ms	50	50	100.00
		spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	11.500m	95.212ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	34.270s	2.289ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	34.270s	2.289ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	16.189m	292.493ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.445m	317.468ms	50	50	100.00
V2	stress_all	spi_device_stress_all	24.948m	135.473ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.170s	46.226us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.180s	71.476us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	8.510s	330.928us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	8.510s	330.928us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.980s	292.615us	5	5	100.00
		spi_device_csr_rw	3.590s	176.438us	20	20	100.00
		spi_device_csr_aliasing	29.140s	2.856ms	5	5	100.00
		spi_device_same_csr_outstanding	6.590s	452.573us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.980s	292.615us	5	5	100.00
		spi_device_csr_rw	3.590s	176.438us	20	20	100.00
		spi_device_csr_aliasing	29.140s	2.856ms	5	5	100.00
		spi_device_same_csr_outstanding	6.590s	452.573us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	2.150s	294.099us	5	5	100.00
		spi_device_tl_intg_err	32.060s	2.155ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	32.060s	2.155ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	12.384m	87.739ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	94.01	98.62	89.36	97.19	95.45	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.98281901303768753278215063550351590042523359210016427433521295760986037615651
Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1190203 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[92])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1190203 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1190203 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[988])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.90749881239077132028187185014466547531138222491358518953848067032503038173012
Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1979879 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[56])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1979879 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1979879 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[952])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.