SPI_DEVICE/1R1W Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.470m	66.628ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.830s	321.930us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.990s	142.943us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.710s	1.397ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	29.680s	5.072ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.600s	157.192us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.990s	142.943us	20	20	100.00
		spi_device_csr_aliasing	29.680s	5.072ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	13.053us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.430s	133.708us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.250s	155.924us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	11.436us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.150s	20.928us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.350s	1.091ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.350s	1.091ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	40.390s	7.145ms	50	50	100.00
		spi_device_tpm_sts_read	1.660s	111.525us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.203m	15.996ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.007m	23.432ms	50	50	100.00
		spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	47.760s	49.874ms	50	50	100.00
		spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	47.760s	49.874ms	50	50	100.00
		spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	1.168m	9.071ms	50	50	100.00
		spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	1.168m	9.071ms	50	50	100.00
		spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	1.168m	9.071ms	50	50	100.00
		spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	1.168m	9.071ms	50	50	100.00
		spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	1.168m	9.071ms	50	50	100.00
		spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.035m	48.081ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.462m	112.508ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.462m	112.508ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.462m	112.508ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.005m	3.023ms	50	50	100.00
		spi_device_read_buffer_direct	25.580s	19.459ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.462m	112.508ms	50	50	100.00
		spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.886m	243.244ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.280s	7.565ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	33.280s	7.565ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.470m	66.628ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.369m	606.651ms	50	50	100.00
V2	stress_all	spi_device_stress_all	25.596m	112.743ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.160s	16.280us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.200s	27.231us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.680s	390.398us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.680s	390.398us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.830s	321.930us	5	5	100.00
		spi_device_csr_rw	3.990s	142.943us	20	20	100.00
		spi_device_csr_aliasing	29.680s	5.072ms	5	5	100.00
		spi_device_same_csr_outstanding	6.430s	1.276ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.830s	321.930us	5	5	100.00
		spi_device_csr_rw	3.990s	142.943us	20	20	100.00
		spi_device_csr_aliasing	29.680s	5.072ms	5	5	100.00
		spi_device_same_csr_outstanding	6.430s	1.276ms	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.980s	458.197us	5	5	100.00
		spi_device_tl_intg_err	25.470s	315.482us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.470s	315.482us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	10.142m	147.138ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.7483509590100727248899485426253328452305117570981135135444136238989641252316
Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1156903 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[31])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1156903 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1156903 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[927])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.50453943477050657665305877940406969219343875858243898481772690737930626678882
Line 63, in log /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4108464 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[31])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4108464 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4108464 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[927])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.