SPI_DEVICE/1R1W Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.535m	138.617ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.730s	47.059us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.920s	500.606us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.170s	1.970ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.980s	4.994ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.630s	95.191us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.920s	500.606us	20	20	100.00
		spi_device_csr_aliasing	20.980s	4.994ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.880s	11.725us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.020s	56.090us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.260s	36.189us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	1.248us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.210s	17.811us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.200s	961.516us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.200s	961.516us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	47.910s	19.166ms	50	50	100.00
		spi_device_tpm_sts_read	1.780s	1.413ms	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.376m	41.634ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	48.010s	19.526ms	50	50	100.00
		spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	59.770s	42.199ms	50	50	100.00
		spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	59.770s	42.199ms	50	50	100.00
		spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	45.360s	4.417ms	50	50	100.00
		spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	45.360s	4.417ms	50	50	100.00
		spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	45.360s	4.417ms	50	50	100.00
		spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	45.360s	4.417ms	50	50	100.00
		spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	45.360s	4.417ms	50	50	100.00
		spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.140s	6.019ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.809m	8.595ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.809m	8.595ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.809m	8.595ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.873m	114.719ms	50	50	100.00
		spi_device_read_buffer_direct	20.390s	1.585ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.809m	8.595ms	50	50	100.00
		spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	11.800m	69.695ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.390s	11.671ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.390s	11.671ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.535m	138.617ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.496m	64.090ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.545m	389.505ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.190s	31.959us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.140s	12.441us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.130s	170.580us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.130s	170.580us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.730s	47.059us	5	5	100.00
		spi_device_csr_rw	2.920s	500.606us	20	20	100.00
		spi_device_csr_aliasing	20.980s	4.994ms	5	5	100.00
		spi_device_same_csr_outstanding	4.110s	373.886us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.730s	47.059us	5	5	100.00
		spi_device_csr_rw	2.920s	500.606us	20	20	100.00
		spi_device_csr_aliasing	20.980s	4.994ms	5	5	100.00
		spi_device_same_csr_outstanding	4.110s	373.886us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.920s	82.116us	5	5	100.00
		spi_device_tl_intg_err	20.390s	2.023ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.390s	2.023ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.836m	94.578ms	48	50	96.00
		TOTAL			1129	1151	98.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.05	98.38	93.99	98.62	89.36	97.19	95.57	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.49233854331971093682162928003263836884907291291723149187441905194734303285234
Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    993484 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[44])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    993484 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    993484 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[940])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.69014401945520432289432785448465931943065680726985513123963982163635929205029
Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    762789 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[8])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    762789 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    762789 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[904])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *

has 2 failures:

Test spi_device_flash_mode_ignore_cmds has 2 failures.

7.spi_device_flash_mode_ignore_cmds.40767230684619456908078242867649249849259152762788419127290019455334719935245
Line 82, in log /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 43146183935 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 46181923588 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/10
  UVM_INFO @ 46181923588 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 5/10
  tl_ul_fuzzy_flash_status_q[i] = 0x8e4488
  UVM_INFO @ 57196751671 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 5/10

23.spi_device_flash_mode_ignore_cmds.3676016747072192002498046067912835408589455130180396079790213134549016929234
Line 90, in log /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 6492014680 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  tl_ul_fuzzy_flash_status_q[i] = 0x219e80
  tl_ul_fuzzy_flash_status_q[i] = 0x219e80
  UVM_INFO @ 6750870680 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 6/8
  UVM_INFO @ 6750870680 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 7/8