SPI_DEVICE/1R1W Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.135m	133.906ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.330s	148.756us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.600s	215.911us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.290s	11.766ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.690s	1.246ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.620s	602.258us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.600s	215.911us	20	20	100.00
		spi_device_csr_aliasing	21.690s	1.246ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.850s	17.953us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.110s	265.728us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.250s	22.202us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	2.124us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.180s	15.661us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.990s	389.082us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.990s	389.082us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	36.090s	6.708ms	50	50	100.00
		spi_device_tpm_sts_read	1.670s	96.854us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.094m	8.617ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.420s	54.072ms	50	50	100.00
		spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.930s	21.779ms	50	50	100.00
		spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.930s	21.779ms	50	50	100.00
		spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	30.600s	8.426ms	50	50	100.00
		spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	30.600s	8.426ms	50	50	100.00
		spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	30.600s	8.426ms	50	50	100.00
		spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	30.600s	8.426ms	50	50	100.00
		spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	30.600s	8.426ms	50	50	100.00
		spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	57.040s	16.321ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.414m	66.095ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.414m	66.095ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.414m	66.095ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	46.640s	23.601ms	50	50	100.00
		spi_device_read_buffer_direct	26.970s	17.880ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.414m	66.095ms	50	50	100.00
		spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.289m	62.037ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	29.580s	2.811ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	29.580s	2.811ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.135m	133.906ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.038m	265.674ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.602m	322.488ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.170s	18.498us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.880s	20.109us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.790s	149.463us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.790s	149.463us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.330s	148.756us	5	5	100.00
		spi_device_csr_rw	2.600s	215.911us	20	20	100.00
		spi_device_csr_aliasing	21.690s	1.246ms	5	5	100.00
		spi_device_same_csr_outstanding	3.990s	179.121us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.330s	148.756us	5	5	100.00
		spi_device_csr_rw	2.600s	215.911us	20	20	100.00
		spi_device_csr_aliasing	21.690s	1.246ms	5	5	100.00
		spi_device_same_csr_outstanding	3.990s	179.121us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.940s	84.446us	5	5	100.00
		spi_device_tl_intg_err	20.150s	2.201ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.150s	2.201ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.767m	71.921ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.56464386511502841614467317993261934064957133033978569577695125611820607582582
Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1265210 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[7])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1265210 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1265210 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[903])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.58637118595791267020034510663829025512792750958899069250023835979107731044199
Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @  20737789 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[2])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @  20737789 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @  20737789 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[898])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.