SPI_DEVICE/1R1W Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.853m	87.874ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.020s	25.205us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.010s	450.464us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.810s	10.021ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.860s	1.220ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.770s	108.182us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.010s	450.464us	20	20	100.00
		spi_device_csr_aliasing	17.860s	1.220ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	30.277us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.450s	59.121us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.290s	33.813us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.170s	2.893us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.710s	15.643us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.470s	286.200us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.470s	286.200us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	37.980s	30.873ms	50	50	100.00
		spi_device_tpm_sts_read	1.850s	107.170us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.119m	9.774ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	45.610s	12.862ms	50	50	100.00
		spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	33.800s	15.854ms	50	50	100.00
		spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	33.800s	15.854ms	50	50	100.00
		spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	50.020s	4.126ms	50	50	100.00
		spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	50.020s	4.126ms	50	50	100.00
		spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	50.020s	4.126ms	50	50	100.00
		spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	50.020s	4.126ms	50	50	100.00
		spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	50.020s	4.126ms	50	50	100.00
		spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	46.540s	13.171ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.907m	27.361ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.907m	27.361ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.907m	27.361ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.764m	6.346ms	50	50	100.00
		spi_device_read_buffer_direct	23.940s	1.163ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.907m	27.361ms	50	50	100.00
		spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.867m	107.228ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.050s	5.879ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.050s	5.879ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.853m	87.874ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.111m	69.040ms	50	50	100.00
V2	stress_all	spi_device_stress_all	23.541m	167.511ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.220s	11.782us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.220s	17.426us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.320s	587.667us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.320s	587.667us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.020s	25.205us	5	5	100.00
		spi_device_csr_rw	4.010s	450.464us	20	20	100.00
		spi_device_csr_aliasing	17.860s	1.220ms	5	5	100.00
		spi_device_same_csr_outstanding	6.140s	561.542us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.020s	25.205us	5	5	100.00
		spi_device_csr_rw	4.010s	450.464us	20	20	100.00
		spi_device_csr_aliasing	17.860s	1.220ms	5	5	100.00
		spi_device_same_csr_outstanding	6.140s	561.542us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.940s	222.732us	5	5	100.00
		spi_device_tl_intg_err	27.610s	3.819ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	27.610s	3.819ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	36.440m	1.500s	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.74	98.65	96.80	99.01	89.36	98.51	95.57	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.54188429969837161686548375734891458844475154427578228261463624002008122906734
Line 63, in log /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1009961 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[46])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1009961 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1009961 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[942])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.62290402118768443828762967122529480366643373786512168791637078799357677043044
Line 63, in log /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2110532 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[63])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2110532 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2110532 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[959])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 46.spi_device_flash_mode_ignore_cmds.101977235682269385414614084991518744921422322887540106962099806642263741156513
    Line 68, in log /workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```