SPI_DEVICE/1R1W Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.201m	45.753ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.110s	45.254us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.870s	154.624us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	19.980s	2.527ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	30.570s	6.061ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.760s	1.001ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.870s	154.624us	20	20	100.00
		spi_device_csr_aliasing	30.570s	6.061ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.120s	24.903us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.720s	113.238us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.380s	24.548us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.190s	1.615us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.190s	19.522us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	9.810s	198.438us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.810s	198.438us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	32.630s	28.802ms	50	50	100.00
		spi_device_tpm_sts_read	1.770s	95.187us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.270m	176.296ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	59.130s	47.786ms	50	50	100.00
		spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.530s	17.617ms	50	50	100.00
		spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.530s	17.617ms	50	50	100.00
		spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	33.410s	2.802ms	50	50	100.00
		spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	33.410s	2.802ms	50	50	100.00
		spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	33.410s	2.802ms	50	50	100.00
		spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	33.410s	2.802ms	50	50	100.00
		spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	33.410s	2.802ms	50	50	100.00
		spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	50.580s	17.099ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.776m	72.342ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.776m	72.342ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.776m	72.342ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.384m	5.713ms	50	50	100.00
		spi_device_read_buffer_direct	25.390s	1.316ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.776m	72.342ms	50	50	100.00
		spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	11.317m	404.032ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	40.600s	12.252ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	40.600s	12.252ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.201m	45.753ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.428m	776.708ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.114m	1.186s	50	50	100.00
V2	alert_test	spi_device_alert_test	1.260s	99.809us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.270s	16.156us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	8.250s	492.688us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	8.250s	492.688us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.110s	45.254us	5	5	100.00
		spi_device_csr_rw	3.870s	154.624us	20	20	100.00
		spi_device_csr_aliasing	30.570s	6.061ms	5	5	100.00
		spi_device_same_csr_outstanding	6.530s	163.833us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.110s	45.254us	5	5	100.00
		spi_device_csr_rw	3.870s	154.624us	20	20	100.00
		spi_device_csr_aliasing	30.570s	6.061ms	5	5	100.00
		spi_device_same_csr_outstanding	6.530s	163.833us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.850s	280.678us	5	5	100.00
		spi_device_tl_intg_err	34.130s	1.093ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	34.130s	1.093ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.947m	116.408ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	98.38	93.99	98.62	89.36	97.19	95.57	99.11

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.70756247627966414890213369282289247166815040727041814137940416741170896341117
      Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1061800 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[25])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1061800 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1061800 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[921])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.42428169935716740927929453065455685739598210518050921210680857621221958169274
      Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    875898 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[87])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    875898 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    875898 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[983])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

Past Results

• Latest
• 2024.09.19_09.08.05
• 2024.09.12_10.19.43
• 2024.09.10_08.14.27
• 2024.09.05_04.24.06
• 2024.09.02_11.33.44
• 2024.08.29_23.15.51
• 2024.08.28_06.59.20