SPI_DEVICE/1R1W Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.895m	47.264ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.980s	34.267us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.490s	70.289us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	43.520s	5.876ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.110s	6.778ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.880s	273.952us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.490s	70.289us	20	20	100.00
		spi_device_csr_aliasing	23.110s	6.778ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.050s	19.949us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.840s	86.654us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.310s	69.166us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	5.080us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.230s	15.886us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.170s	499.201us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.170s	499.201us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	38.760s	7.278ms	50	50	100.00
		spi_device_tpm_sts_read	1.940s	182.430us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.179m	48.708ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	46.950s	176.502ms	50	50	100.00
		spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.400s	7.895ms	50	50	100.00
		spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.400s	7.895ms	50	50	100.00
		spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	34.290s	9.861ms	50	50	100.00
		spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	34.290s	9.861ms	50	50	100.00
		spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	34.290s	9.861ms	50	50	100.00
		spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	34.290s	9.861ms	50	50	100.00
		spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	34.290s	9.861ms	50	50	100.00
		spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.333m	19.265ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.282m	42.777ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.282m	42.777ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.282m	42.777ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.033m	3.252ms	50	50	100.00
		spi_device_read_buffer_direct	27.920s	2.310ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.282m	42.777ms	50	50	100.00
		spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.037m	63.249ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.600s	3.811ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	28.600s	3.811ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.895m	47.264ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.594m	162.851ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.637m	764.142ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.190s	53.470us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.210s	25.909us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.670s	1.900ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.670s	1.900ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.980s	34.267us	5	5	100.00
		spi_device_csr_rw	3.490s	70.289us	20	20	100.00
		spi_device_csr_aliasing	23.110s	6.778ms	5	5	100.00
		spi_device_same_csr_outstanding	6.190s	161.547us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.980s	34.267us	5	5	100.00
		spi_device_csr_rw	3.490s	70.289us	20	20	100.00
		spi_device_csr_aliasing	23.110s	6.778ms	5	5	100.00
		spi_device_same_csr_outstanding	6.190s	161.547us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	2.050s	290.000us	5	5	100.00
		spi_device_tl_intg_err	25.560s	3.408ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.560s	3.408ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.316m	94.350ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.74	98.65	96.80	99.01	89.36	98.51	95.57	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.29388523076733207557052020701878083539859855934986548448426567762151767004127
Line 63, in log /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    715690 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[58])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    715690 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    715690 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[954])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.107609653798122477400421459970157325362614006642471622887820243879906318113253
Line 63, in log /workspaces/repo/scratch/os_regression_2024_10_11/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4359509 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[99])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4359509 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4359509 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[995])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.