SPI_DEVICE/1R1W Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.212m	1.496s	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.250s	44.766us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.900s	75.092us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.890s	1.246ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	34.320s	4.957ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	6.320s	109.635us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.900s	75.092us	20	20	100.00
		spi_device_csr_aliasing	34.320s	4.957ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.100s	25.543us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.850s	271.279us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.410s	25.616us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.240s	1.076us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.350s	16.919us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.480s	159.115us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.480s	159.115us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	40.130s	7.312ms	50	50	100.00
		spi_device_tpm_sts_read	1.880s	258.062us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	59.080s	32.111ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	42.300s	35.446ms	50	50	100.00
		spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	32.710s	32.337ms	50	50	100.00
		spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	32.710s	32.337ms	50	50	100.00
		spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	49.640s	3.891ms	50	50	100.00
		spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	49.640s	3.891ms	50	50	100.00
		spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	49.640s	3.891ms	50	50	100.00
		spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	49.640s	3.891ms	50	50	100.00
		spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	49.640s	3.891ms	50	50	100.00
		spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	51.520s	21.330ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.595m	52.737ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.595m	52.737ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.595m	52.737ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	58.290s	17.158ms	50	50	100.00
		spi_device_read_buffer_direct	23.440s	3.098ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.595m	52.737ms	50	50	100.00
		spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.032m	585.354ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.300s	2.239ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.300s	2.239ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.212m	1.496s	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.243m	377.186ms	50	50	100.00
V2	stress_all	spi_device_stress_all	15.096m	77.483ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.320s	14.713us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.330s	15.670us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.090s	818.328us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.090s	818.328us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.250s	44.766us	5	5	100.00
		spi_device_csr_rw	3.900s	75.092us	20	20	100.00
		spi_device_csr_aliasing	34.320s	4.957ms	5	5	100.00
		spi_device_same_csr_outstanding	6.140s	829.374us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.250s	44.766us	5	5	100.00
		spi_device_csr_rw	3.900s	75.092us	20	20	100.00
		spi_device_csr_aliasing	34.320s	4.957ms	5	5	100.00
		spi_device_same_csr_outstanding	6.140s	829.374us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.960s	560.053us	5	5	100.00
		spi_device_tl_intg_err	28.420s	1.691ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	28.420s	1.691ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.286m	59.490ms	49	50	98.00
		TOTAL			1130	1151	98.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	98.38	94.01	98.62	89.36	97.19	95.57	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.25184429429130303932030181674648622266636180086836175511461699665292602453148
Line 63, in log /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4684017 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[101])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4684017 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4684017 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[997])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.110353583923734539627674868700057118259271267082845832312647892445188927668985
Line 63, in log /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    722070 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[41])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    722070 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    722070 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[937])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 37.spi_device_flash_mode_ignore_cmds.107585993180011852981575126547479016024217275603704114697878510073974998490497
    Log /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```