SPI_DEVICE/2P Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.780s	603.618us	0	50	0.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	171.967us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.660s	110.839us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.230s	3.615ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.130s	1.361ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.930s	787.320us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.660s	110.839us	20	20	100.00
		spi_device_csr_aliasing	25.130s	1.361ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	39.069us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.100s	448.344us	5	5	100.00
V1		TOTAL			65	115	56.52
V2	csb_read	spi_device_csb_read	0.810s	20.257us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	119.375us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.770s	45.127us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	14.170s	1.821ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	14.170s	1.821ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	36.090s	51.966ms	50	50	100.00
		spi_device_tpm_sts_read	1.160s	628.158us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.152m	28.256ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	47.120s	20.771ms	50	50	100.00
		spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	51.500s	20.412ms	50	50	100.00
		spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	51.500s	20.412ms	50	50	100.00
		spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	cmd_info_slots	spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	cmd_read_status	spi_device_intercept	42.020s	3.314ms	43	50	86.00
		spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	cmd_read_jedec	spi_device_intercept	42.020s	3.314ms	43	50	86.00
		spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	cmd_read_sfdp	spi_device_intercept	42.020s	3.314ms	43	50	86.00
		spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	cmd_fast_read	spi_device_intercept	42.020s	3.314ms	43	50	86.00
		spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	cmd_read_pipeline	spi_device_intercept	42.020s	3.314ms	43	50	86.00
		spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	flash_cmd_upload	spi_device_upload	43.400s	14.196ms	31	50	62.00
V2	mailbox_command	spi_device_mailbox	3.474m	91.345ms	41	50	82.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.474m	91.345ms	41	50	82.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.474m	91.345ms	41	50	82.00
V2	cmd_read_buffer	spi_device_flash_mode	2.919m	54.355ms	45	50	90.00
		spi_device_read_buffer_direct	22.750s	9.147ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.474m	91.345ms	41	50	82.00
		spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	quad_spi	spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	dual_spi	spi_device_flash_all	21.240s	15.233ms	0	50	0.00
V2	4b_3b_feature	spi_device_cfg_cmd	20.440s	8.152ms	25	50	50.00
V2	write_enable_disable	spi_device_cfg_cmd	20.440s	8.152ms	25	50	50.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.780s	603.618us	0	50	0.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.610s	401.006us	0	50	0.00
V2	stress_all	spi_device_stress_all	35.970s	14.899ms	15	50	30.00
V2	alert_test	spi_device_alert_test	0.770s	15.405us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	68.538us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.820s	533.619us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.820s	533.619us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	171.967us	5	5	100.00
		spi_device_csr_rw	2.660s	110.839us	20	20	100.00
		spi_device_csr_aliasing	25.130s	1.361ms	5	5	100.00
		spi_device_same_csr_outstanding	4.340s	862.776us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	171.967us	5	5	100.00
		spi_device_csr_rw	2.660s	110.839us	20	20	100.00
		spi_device_csr_aliasing	25.130s	1.361ms	5	5	100.00
		spi_device_same_csr_outstanding	4.340s	862.776us	20	20	100.00
V2		TOTAL			780	980	79.59
V2S	tl_intg_err	spi_device_sec_cm	1.210s	115.241us	5	5	100.00
		spi_device_tl_intg_err	22.980s	878.289us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.980s	878.289us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			870	1120	77.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	14	63.64
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.05	97.56	92.93	98.61	80.85	95.95	90.92	87.54

Failure Buckets

Job spi_device_2p-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 208 failures:
- Test spi_device_mailbox has 9 failures.
  - 0.spi_device_mailbox.66532067841801075359278114479271043278378038465327746742569804945500390314697
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest/run.log
```
  Job ID: smart:1fd0a242-8198-43be-8b52-0f5f3fcba192
```
  - 9.spi_device_mailbox.106555817659875619383099834702895681401598309001512229516399029679493413008342
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest/run.log
```
  Job ID: smart:15319ab3-0208-46f6-b21e-ecf271d45d57
```
  - ... and 7 more failures.
- Test spi_device_flash_all has 44 failures.
  - 0.spi_device_flash_all.87271644916831636459329722022278791040282507124192608365917028222376690898071
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
```
  Job ID: smart:35fcb86c-4912-4025-9941-9a94e7350b6b
```
  - 1.spi_device_flash_all.78213151341699846764915611581185598336004894704955032773893489017953744552297
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
```
  Job ID: smart:d0ff18b0-03ba-40f4-b97d-4923bfe96085
```
  - ... and 42 more failures.
- Test spi_device_flash_and_tpm has 48 failures.
  - 0.spi_device_flash_and_tpm.106597971890237710589878903389442764871061093303224927904964683050252019476567
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:7291ef37-874b-40fc-982a-83fc32842b17
```
  - 1.spi_device_flash_and_tpm.5019305756871403708467942032920513421402897310098867997943687539274733845412
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
```
  Job ID: smart:79ccb18e-0314-4ad0-86ef-ef4daa8153df
```
  - ... and 46 more failures.
- Test spi_device_flash_and_tpm_min_idle has 45 failures.
  - 0.spi_device_flash_and_tpm_min_idle.55186755511750516963647030855501757769789513636813008470369521579051445369749
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:ff56a903-a6aa-402c-a20a-22ae7e25781d
```
  - 1.spi_device_flash_and_tpm_min_idle.113960684506653516790644893914948168595356304246715434983405056760716587580257
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  Job ID: smart:0f4b4a87-58f3-49a3-bc27-fcb6e04f2cf0
```
  - ... and 43 more failures.
- Test spi_device_cfg_cmd has 19 failures.
  - 1.spi_device_cfg_cmd.7596178076888426643037069873888850914719563323828932961816375329345289845140
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
```
  Job ID: smart:a1b02b0b-6e9a-45bd-ba1f-ee13dc98ad1a
```
  - 6.spi_device_cfg_cmd.12297243540149359766882251312304147166889924865142133007261404410251638444867
    Log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest/run.log
```
  Job ID: smart:3d4863e9-c707-41dd-8bc6-1e9bfb419d77
```
  - ... and 17 more failures.
- ... and 3 more tests.

UVM_ERROR (spi_device_scoreboard.sv:1298) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 21 failures:

Test spi_device_cfg_cmd has 5 failures.

0.spi_device_cfg_cmd.101875759116334192303725945141150098077065047514059549038115741362441755350190
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 395938164 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1cf3c6) != exp '{'{other_status:'h73cf1, wel:'h0, busy:'h0}, '{other_status:'h73cf1, wel:'h0, busy:'h0}}
  UVM_ERROR @ 397738164 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1cf3c6) != exp '{'{other_status:'h73cf1, wel:'h0, busy:'h0}, '{other_status:'h73cf1, wel:'h0, busy:'h0}}
  UVM_ERROR @ 398778164 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1cf3c6) != exp '{'{other_status:'h73cf1, wel:'h0, busy:'h0}, '{other_status:'h73cf1, wel:'h0, busy:'h0}}
  UVM_INFO @ 399738164 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0xe9
  UVM_ERROR @ 400978164 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1cf3c6) != exp '{'{other_status:'h73cf1, wel:'h0, busy:'h0}, '{other_status:'h73cf1, wel:'h0, busy:'h0}}

9.spi_device_cfg_cmd.95540020332256804381958219819844727696659708242033825002851378941999836444976
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @  44864649 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @  47755936 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x4
  UVM_ERROR @  48060282 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcc7076) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h331c1d, wel:'h0, busy:'h0}, '{other_status:'h331c1d, wel:'h0, busy:'h0}}
  UVM_INFO @  52799384 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0x4
  UVM_INFO @  57538486 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 3, test op = 0xb7

... and 3 more failures.

Test spi_device_upload has 12 failures.

5.spi_device_upload.16211762884056746513938958733127213680248695332524429203436444350404597519162
Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_upload/latest/run.log

  UVM_ERROR @ 735227142 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 737117142 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 749077142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.spi_device_upload.65236506810295674130918634557633546015351488231235098479510391196767785461903
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/6.spi_device_upload/latest/run.log

  UVM_ERROR @ 310495870 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 439368808 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 440899953 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 2, test op = 0x5a
  UVM_INFO @ 615015334 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 3, test op = 0xbb
  UVM_INFO @ 619693425 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 4, test op = 0xf8

... and 10 more failures.

Test spi_device_stress_all has 2 failures.

10.spi_device_stress_all.100434926710530894493027527177258182604873753191261326185683712158632506066822
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 9965173340 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 9984068447 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 9984068447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.spi_device_stress_all.13365679604262081959487177743375642462748352837385997466970568588834331421522
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 3811594555 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 3840244514 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3840244514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm has 2 failures.

24.spi_device_flash_and_tpm.99182950310201654846191161652026921517204348727308828485936587808993021892958
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 599583090 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 603618256 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 603618256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.spi_device_flash_and_tpm.44166679897171833073897678445600387441525921144101207566730775647330701639025
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 241949870 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_FATAL @ 348464049 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 348464049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_device_scoreboard.sv:726) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 18 failures:

Test spi_device_stress_all has 2 failures.

3.spi_device_stress_all.63123226947148282634069368732424248320388934522010236790424441959623667950488
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest/run.log

  UVM_FATAL @ 14898913770 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 14898913770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.spi_device_stress_all.71774948212766930409239329769631009592936793831720700582152772976584123779280
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest/run.log

  UVM_FATAL @  54857950 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  54857950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_upload has 7 failures.

4.spi_device_upload.46840563683910949876598070258384366622578275191012961292519460612936857748159
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/4.spi_device_upload/latest/run.log

  UVM_FATAL @ 317597582 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 317597582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.spi_device_upload.53721977083898457646431234920389249854851458215739060657981021601510173769264
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_upload/latest/run.log

  UVM_FATAL @  25157289 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  25157289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test spi_device_flash_all has 6 failures.

10.spi_device_flash_all.74072464430386163860603275807575750859005508878482595069125712213573796843222
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest/run.log

  UVM_FATAL @ 15232556109 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 15232556109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.spi_device_flash_all.96386488034461335177686228587083699924317120076350174852090546728078363056693
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest/run.log

  UVM_FATAL @ 535870203 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 535870203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test spi_device_flash_and_tpm_min_idle has 3 failures.
- 17.spi_device_flash_and_tpm_min_idle.108335678163648290664239905612396475424898893100865246722199992701462668167261
  Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @  81117461 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  81117461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- 41.spi_device_flash_and_tpm_min_idle.110365578904823328105980938807323694691243563434869665450649890626194825650355
  Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @  64536226 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  64536226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- ... and 1 more failures.

Test spi_device_cfg_cmd has 1 failures.

5.spi_device_cfg_cmd.29087652668158021524933515655189946788020370720262019566932609444917391951971
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 3308622581 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1527ca) != exp '{'{other_status:'h2a5a15, wel:'h0, busy:'h0}, '{other_status:'h549f2, wel:'h0, busy:'h0}, '{other_status:'h549f2, wel:'h0, busy:'h0}}
  UVM_ERROR @ 3309473661 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1527ca) != exp '{'{other_status:'h2a5a15, wel:'h0, busy:'h0}, '{other_status:'h549f2, wel:'h0, busy:'h0}, '{other_status:'h549f2, wel:'h0, busy:'h0}}
  UVM_ERROR @ 3309814093 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1527ca) != exp '{'{other_status:'h2a5a15, wel:'h0, busy:'h0}, '{other_status:'h549f2, wel:'h0, busy:'h0}, '{other_status:'h549f2, wel:'h0, busy:'h0}}
  UVM_ERROR @ 3311069436 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1527ca) != exp '{'{other_status:'h2a5a15, wel:'h0, busy:'h0}, '{other_status:'h549f2, wel:'h0, busy:'h0}, '{other_status:'h20bfd5, wel:'h0, busy:'h0}, '{other_status:'h20bfd5, wel:'h0, busy:'h0}}
  UVM_ERROR @ 3323644143 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1527ca) != exp '{'{other_status:'h2a5a15, wel:'h0, busy:'h0}, '{other_status:'h549f2, wel:'h0, busy:'h0}, '{other_status:'h20bfd5, wel:'h0, busy:'h0}, '{other_status:'h20bfd5, wel:'h0, busy:'h0}}

Test spi_device_flash_and_tpm_min_idle has 1 failures.

31.spi_device_flash_and_tpm_min_idle.86820168390645972919967093399503365758584575819210145146689706230360544622383
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 115000417 ps: (spi_device_scoreboard.sv:1298) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h38150f, wel:'h0, busy:'h0}}
  UVM_FATAL @ 126074391 ps: (spi_device_scoreboard.sv:726) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 126074391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:969) scoreboard [scoreboard] WEL mismatch: act=*, pred_fuzzy_q ('{'{other_status:*, wel:*, busy:*}} ) pred=* has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

24.spi_device_flash_and_tpm_min_idle.34139842320048678666629357587666201969428714983656483165356677323505870285044
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 392838966 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h71d21, wel:'h0, busy:'h0}} ) pred=0x0
  UVM_ERROR @ 393005638 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h71d21, wel:'h0, busy:'h0}} ) pred=0x0
  UVM_ERROR @ 393172310 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h71d21, wel:'h0, busy:'h0}} ) pred=0x0
  UVM_ERROR @ 393338982 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h71d21, wel:'h0, busy:'h0}} ) pred=0x0
  UVM_ERROR @ 393505654 ps: (spi_device_scoreboard.sv:969) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] WEL mismatch: act=0x1, pred_fuzzy_q ('{'{other_status:'h71d21, wel:'h0, busy:'h0}} ) pred=0x0