SPI_DEVICE/2P Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.395m	68.433ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.820s	43.171us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.420s	99.811us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.450s	2.708ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.270s	4.106ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.250s	603.084us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.420s	99.811us	20	20	100.00
		spi_device_csr_aliasing	20.270s	4.106ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.020s	16.865us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.900s	73.231us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.270s	18.410us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.680s	35.304us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	31.397us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	14.290s	1.215ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	14.290s	1.215ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	35.410s	25.540ms	50	50	100.00
		spi_device_tpm_sts_read	1.710s	355.946us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.038m	69.743ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.320m	33.303ms	50	50	100.00
		spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	37.830s	46.895ms	50	50	100.00
		spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	37.830s	46.895ms	50	50	100.00
		spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	36.820s	3.649ms	50	50	100.00
		spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	36.820s	3.649ms	50	50	100.00
		spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	36.820s	3.649ms	50	50	100.00
		spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	36.820s	3.649ms	50	50	100.00
		spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	36.820s	3.649ms	50	50	100.00
		spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	56.830s	43.658ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.278m	215.034ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.278m	215.034ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.278m	215.034ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.403m	48.512ms	50	50	100.00
		spi_device_read_buffer_direct	19.620s	1.282ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.278m	215.034ms	50	50	100.00
		spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.186m	95.827ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	30.500s	34.796ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	30.500s	34.796ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.395m	68.433ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.441m	47.748ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.364m	100.253ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.170s	13.457us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.150s	18.655us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.500s	221.030us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.500s	221.030us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.820s	43.171us	5	5	100.00
		spi_device_csr_rw	3.420s	99.811us	20	20	100.00
		spi_device_csr_aliasing	20.270s	4.106ms	5	5	100.00
		spi_device_same_csr_outstanding	4.920s	229.984us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.820s	43.171us	5	5	100.00
		spi_device_csr_rw	3.420s	99.811us	20	20	100.00
		spi_device_csr_aliasing	20.270s	4.106ms	5	5	100.00
		spi_device_same_csr_outstanding	4.920s	229.984us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.960s	310.856us	5	5	100.00
		spi_device_tl_intg_err	22.170s	1.777ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.170s	1.777ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.443m	133.688ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.44	94.08	98.62	89.36	97.28	95.43	99.26

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *

has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

48.spi_device_flash_mode_ignore_cmds.15292043212433624005458845344762268634857760458544847736209066627052663062339
Line 80, in log /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 1517197253 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 1519366408 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/14
  UVM_INFO @ 1519366408 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 4/14
  UVM_INFO @ 2006998550 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/14
  UVM_INFO @ 2006998550 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 5/14