SPI_DEVICE/2P Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.273m	306.911ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.090s	42.196us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.530s	92.951us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.120s	6.011ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	28.590s	965.833us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.340s	1.523ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.530s	92.951us	20	20	100.00
		spi_device_csr_aliasing	28.590s	965.833us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.050s	31.266us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.070s	219.243us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.270s	23.527us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.590s	62.374us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.920s	16.340us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.890s	1.064ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.890s	1.064ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	37.540s	7.458ms	50	50	100.00
		spi_device_tpm_sts_read	1.460s	253.964us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.163m	10.544ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	47.080s	101.553ms	50	50	100.00
		spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	49.940s	42.153ms	50	50	100.00
		spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	49.940s	42.153ms	50	50	100.00
		spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.810s	8.911ms	50	50	100.00
		spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.810s	8.911ms	50	50	100.00
		spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.810s	8.911ms	50	50	100.00
		spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.810s	8.911ms	50	50	100.00
		spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.810s	8.911ms	50	50	100.00
		spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	46.750s	21.640ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.607m	55.446ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.607m	55.446ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.607m	55.446ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.044m	11.201ms	50	50	100.00
		spi_device_read_buffer_direct	20.720s	3.366ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.607m	55.446ms	50	50	100.00
		spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	12.005m	89.733ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	29.350s	24.050ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	29.350s	24.050ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.273m	306.911ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.608m	400.494ms	50	50	100.00
V2	stress_all	spi_device_stress_all	18.995m	229.831ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.180s	14.300us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.170s	21.044us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	8.290s	1.392ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	8.290s	1.392ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.090s	42.196us	5	5	100.00
		spi_device_csr_rw	3.530s	92.951us	20	20	100.00
		spi_device_csr_aliasing	28.590s	965.833us	5	5	100.00
		spi_device_same_csr_outstanding	5.420s	410.428us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.090s	42.196us	5	5	100.00
		spi_device_csr_rw	3.530s	92.951us	20	20	100.00
		spi_device_csr_aliasing	28.590s	965.833us	5	5	100.00
		spi_device_same_csr_outstanding	5.420s	410.428us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.090s	182.683us	5	5	100.00
		spi_device_tl_intg_err	21.520s	899.525us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.520s	899.525us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.014m	122.726ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	98.45	94.10	98.62	89.36	97.29	95.56	99.21

Past Results

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