SPI_DEVICE/2P Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.689m	317.411ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.550s	39.325us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.930s	123.805us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.710s	22.549ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.690s	1.794ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.990s	106.354us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.930s	123.805us	20	20	100.00
		spi_device_csr_aliasing	14.690s	1.794ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.970s	33.202us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.790s	25.059us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.250s	21.171us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.630s	33.912us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.660s	17.208us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.370s	570.991us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.370s	570.991us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	35.740s	32.562ms	50	50	100.00
		spi_device_tpm_sts_read	1.710s	114.923us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.159m	75.717ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	49.220s	9.751ms	50	50	100.00
		spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	56.880s	150.124ms	50	50	100.00
		spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	56.880s	150.124ms	50	50	100.00
		spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	38.290s	3.336ms	50	50	100.00
		spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	38.290s	3.336ms	50	50	100.00
		spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	38.290s	3.336ms	50	50	100.00
		spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	38.290s	3.336ms	50	50	100.00
		spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	38.290s	3.336ms	50	50	100.00
		spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	50.760s	31.040ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.876m	48.848ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.876m	48.848ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.876m	48.848ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.065m	16.395ms	50	50	100.00
		spi_device_read_buffer_direct	33.980s	2.581ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.876m	48.848ms	50	50	100.00
		spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.057m	319.477ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	17.220s	7.207ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	17.220s	7.207ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.689m	317.411ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.311m	67.387ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.986m	415.708ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.160s	12.521us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.130s	73.435us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.340s	223.549us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.340s	223.549us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.550s	39.325us	5	5	100.00
		spi_device_csr_rw	2.930s	123.805us	20	20	100.00
		spi_device_csr_aliasing	14.690s	1.794ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	980.886us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.550s	39.325us	5	5	100.00
		spi_device_csr_rw	2.930s	123.805us	20	20	100.00
		spi_device_csr_aliasing	14.690s	1.794ms	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	980.886us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.780s	90.141us	5	5	100.00
		spi_device_tl_intg_err	21.660s	1.228ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.660s	1.228ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.930m	246.218ms	50	50	100.00
		TOTAL			1151	1151	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.77	98.70	96.89	99.01	89.36	98.59	95.56	99.26

Past Results

• Latest
• 2024.10.10_10.18.46
• 2024.10.04_00.45.36
• 2024.09.25_11.04.39
• 2024.09.19_09.08.18
• 2024.09.12_10.19.56
• 2024.09.10_08.14.39
• 2024.09.05_04.24.19