SPI_DEVICE/2P Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.261m	57.704ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.150s	147.124us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.960s	366.888us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.190s	2.085ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	27.850s	6.008ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.710s	61.693us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.960s	366.888us	20	20	100.00
		spi_device_csr_aliasing	27.850s	6.008ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.110s	17.651us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.430s	28.859us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.360s	27.254us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.730s	82.758us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.160s	45.916us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	11.480s	296.968us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.480s	296.968us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	44.230s	42.697ms	50	50	100.00
		spi_device_tpm_sts_read	1.870s	101.570us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.321m	33.391ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.070s	10.828ms	50	50	100.00
		spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	55.850s	12.165ms	50	50	100.00
		spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	55.850s	12.165ms	50	50	100.00
		spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	59.110s	28.397ms	50	50	100.00
		spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	59.110s	28.397ms	50	50	100.00
		spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	59.110s	28.397ms	50	50	100.00
		spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	59.110s	28.397ms	50	50	100.00
		spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	59.110s	28.397ms	50	50	100.00
		spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.243m	12.231ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.385m	54.673ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.385m	54.673ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.385m	54.673ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	44.570s	9.336ms	50	50	100.00
		spi_device_read_buffer_direct	25.630s	8.552ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.385m	54.673ms	50	50	100.00
		spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.250m	45.699ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	32.530s	3.676ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	32.530s	3.676ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.261m	57.704ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.447m	58.359ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.575m	67.916ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.280s	42.516us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.290s	32.073us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	7.150s	211.435us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	7.150s	211.435us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.150s	147.124us	5	5	100.00
		spi_device_csr_rw	3.960s	366.888us	20	20	100.00
		spi_device_csr_aliasing	27.850s	6.008ms	5	5	100.00
		spi_device_same_csr_outstanding	6.550s	162.960us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.150s	147.124us	5	5	100.00
		spi_device_csr_rw	3.960s	366.888us	20	20	100.00
		spi_device_csr_aliasing	27.850s	6.008ms	5	5	100.00
		spi_device_same_csr_outstanding	6.550s	162.960us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.850s	57.037us	5	5	100.00
		spi_device_tl_intg_err	29.000s	1.016ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	29.000s	1.016ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	10.212m	164.871ms	49	50	98.00
		TOTAL			1150	1151	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	22	22	22	100.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	98.44	94.08	98.62	89.36	97.27	95.56	99.26

Failure Buckets

• UVM_ERROR (spi_device_pass_base_vseq.sv:704) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 29.spi_device_flash_mode_ignore_cmds.6454008304620849981593066082818070702260542382661947332895661641733119979726
      Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_2p-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 2334146628 ps: (spi_device_pass_base_vseq.sv:704) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        tl_ul_fuzzy_flash_status_q[i] = 0x2bd4e8
        tl_ul_fuzzy_flash_status_q[i] = 0x2bd4e8
        tl_ul_fuzzy_flash_status_q[i] = 0xdbaa7c
        tl_ul_fuzzy_flash_status_q[i] = 0xdbaa7c
      

Past Results

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